Arcom SC88T, Technical Manual

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Table 1. (continued)
The SC88T can be jumpered either to act as a potential master which requests
the bus from the permanent master or a separate arbiter, or it can be set up to
ignore arbitration. If the SC88T is set to ignore arbitration it must be the only
master on the bus. If you wish to use more than one master on the bus, then you
must have one and only one arbiter. A suitable arbiter is available on the
SYSCON board. See ‘Links and Options’ for details of how to set up the board.
Key: * = signal is active low
3s = tri-dtate
tp = totem-pole
o/c = open-collector
It is quite easy to use the SC88T on the STEbus. You will need a terminated
backplane, and one or more slave boards, such as A/D converters, for example.
In order to comply fully with the specification of the impedance of each
backplane line should be 60 ohms ±10%. However, a short backplane is not
likely to cause any malfunction even if its impedance varies considerably from
this. A terminator is necessary because some of the lines are open-collector, and
timing is critical on the strobes.
A SC88T configured as standard will generate all necessary bus signals. All that
is required to generate a bus access is that you try to read from or write to a
memory or I/O location which the on-board logic defines as on the bus. See the
‘Memory Map’ and ‘I/O Devices’ sections for details on which addresses are on-
board and which are not.
Note: The internal timers on the SC88T can be programmed so that if the slave
board which you are attempting to access does not respond, for example if you
used the wrong address, a bus timeout will be generated. This will release the
SC88T from its wait-state and generate an interrupt.
See section 7. for more details.
J90 SC88T
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2192-08819-000-000
Signal
BUSRQ0-1*
BUSAK0-1*
0
I
o/c
in
Bus requests
Bus Acknowledge
Potential (temporary) bus masters request the
bus from the arbiter on either of these lines.
BUSRQ0* has a higher priority than
BUSRQ1*.
The SC88T acts as temporary master, and can
be jumpered to ignore arbitration as a single
master.
The arbiter acknowledges a request from
either of the two potential masters on these
lines. A potential master may only drive the
bus when it has received an acknowledge on
the line corresponding to its request.
In-Out Type Description Implementation