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Appendix D. Example Programs.

Page 23

J90 SC88T

2192-08819-000-000

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Summary of Contents for SC88T

Page 1: ...ion 4 Links and Options 10 Section 5 I O Devices 13 Section 6 Memory Map 15 Section 7 Using the SC88T 17 Appendix A Component List 19 Appendix B Connections 20 Appendix C Specification 22 Appendix D Example Program 23 Appendix E Circuit Diagram 30 Page 1 J90 SC88T 2192 08819 000 000 SC88T STE 80188 CPU Technical Manual ...

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Page 3: ...ful contact information Customer Support tel 44 0 1223 412428 fax 44 0 1223 403400 email support arcom co uk Sales tel 44 0 1223 411200 fax 44 0 1223 410457 email sales arcom co uk or for the US icpsales arcomcontrols com United Kingdom Arcom Control Systems Ltd Clifton Road Cambridge CB1 4WH UK tel 44 0 1223 411200 fax 44 0 1223 410457 FoD 01223 240600 United States Arcom Control Systems Inc 1351...

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Page 5: ...Contact us for details The STEbus interface is an important feature of the SC88T The bus is being ratified by the IEEE IEEE designation is P1000 and it is designed as a processor and manufacturer independent asynchronous multiprocessing bus The asynchronous nature of the bus means that a slave board memory or I O must acknowledge commands by the SC88T which will wait until it does so that any spee...

Page 6: ...top 4 bits of the CPU address bus and IC7 latches the lowest eight bits IC11 controls chip selects for the RAMs IC15 17 and generates a one bit output port for use as an attention request on the STEbus The EPROMs IC14 and 16 can be 8 16 32 or 64k each and there are 2 jumpers to set the EPROM size Address and data lines on the bus are driven by IC1 2 4 and 5 with IC5 driving the strobes Incoming bu...

Page 7: ...knowledge cycles It does respond to bus non vectored interrupts on lines ATNRQ0 ATNRQ3 if they have been appropriately jumpered Driven by the CPU on write cycles or by the slave on read cycles Addresses data and command modifiers are valid before the falling edge of ADRSTB and DATSTB Both strobes are active at the same time on the SC88T On the write cycle valid data and CM0 are present before this...

Page 8: ...robes A SC88T configured as standard will generate all necessary bus signals All that is required to generate a bus access is that you try to read from or write to a memory or I O location which the on board logic defines as on the bus See the Memory Map and I O Devices sections for details on which addresses are on board and which are not Note The internal timers on the SC88T can be programmed so...

Page 9: ... If DATACK or TFRERR have not been received Bus timeout Check that the slave board can respond to the bus access which the SC88T sent out If it can check the SYSCLK is present on the bus as many slave boards require this for timing and check also that SYSCLK is coming from only one source if you have more than one CPU on the bus Check also that your software has allowed bus timeouts to occur and t...

Page 10: ...SC88T Page 10 2192 08819 000 000 TP3 TP4 LK5 PL2 TP1 TP8 LK6 A B A B A B A B A B LK7 LK9 LK8 TP9 TP10 TP11 A B TP6 TP7 LK4 LK2 LK1 A B C A B C D E A B C D E LK3 1 2 1 2 PL1 PL3 LK10 TP2 TP5 LK1A1 LK1A2 LK1B1 LK1B2 LK1C1 LK1C2 LK1D1 LK1D2 LK1E1 LK1E2 LK1DE2 ATOUT to ATNRQ1 ATNRQ1 goes to CPU INT0 ATOUT to ATNRQ2 ATNRQ2 goes to CPU INT1 ATOUT to ATNRQ3 ATNRQ3 goes to CPU INT3 ATOUT to ATNRQ5 ATNRQ5 ...

Page 11: ...2 08819 000 000 LK2A LK2B1 LK2B2 LK2C1 LK2C2 LK2D1 LK2D2 LK2E SYSRST to bus from this board Accept bus acknowledges from external arbiter Ignore arbitration single master only Bus requests on BUSRQ1 Bus requests on BUSRQ0 Bus acknowledges on BUSACK1 Bus acknowledges on BUSACK0 SYSCLK from this board LK3A LK3B LK3C NMI disabled NMI from ANRQ0 NMI from TFRERR LK4 open LK4 made 8k RAM chips installed...

Page 12: ...7B EPROMs pin 1 to 5V all except 27512 EPROMs pin 1 to A15 27512 only EPROMs pin 27 to 5V 2764 27128 EPROMs pin 27 to A14 27256 27512 LK8A LK8B LK9A LK9B NB LK9 Dependant on LK8 RAM power is from STEbus VSTBY line RAM power is from on board 5V RAM pin 26 to 5V 8k RAMs or VSTBY RAM pin 26 to A13 32k RAMs Figure 7 Link areas 6 and 7 o o 7A 6A o o 7B 6B o o Figure 8 Link areas 8 and 9 o o 9A 8A o o 9...

Page 13: ... controlled by two programmable chip selects PCS1 is the chip select which accesses the registers Accessing PCS2 will assert INTA the SCC interrupt acknowledge input This must be done to acknowledge the SCC interrupt generated on INT2 of the 80188 because the 80188 in its most useful interrupt mode does not generate an acknowledge A read from PCS2 will read the interrupt vector from the SCC and re...

Page 14: ...F00 20 to 3E 50 to 56 58 to 5E 60 to 66 A0 A2 A4 A6 A8 C0 to CA D0 to DA FE UMCS LMCS PACS MMCS MPCS Interrupt Controller Timer 0 Control Timer 1 Control Timer 2 Control Upper Memory Chip Select Lower Memory Chip Select Peripheral Base Address Control Middle Memory Chip Select Middle Peripheral Chip Select DMA Descriptors Channel 0 DMA Descriptors Channel 1 Relocation register Control Block regist...

Page 15: ... UCS and MCSO 3 Two wait states will be required by slow EPROMs If STEbus memory overlaps MCS1 and MCS0 then MCS0 3 must accept externally generated wait states until DATACK is received from the bus Both the above conditions are satisfied by the contents of the table below Slow EPROMs are those of 250ns access time and above Note that Arcom use two wait states in their initialisation code This all...

Page 16: ...S1 and MCS3 are not used To ensure that they do not interfere with STE memory space set UCS and MCS0 3 to include externally generated wait states So that accesses to memory in the MCS0 and MCS1 address ranges wait for the DATACK signal from the STEbus Example shown with two 8k RAMs as supplied plus two 32k EPROMs J90 SC88T Page 16 2192 08819 000 000 Example memory map using two 32k EPROMs If EPRO...

Page 17: ...pheral chip selects must be programmed to allow access to the on board SCC Timers 0 and 1 may be programmed to produce a bus timeout function The input to T0 is the bus driver enable line T0 output is wired to T1 input and T1 output going low will take the CPU out of the wait state For this to happen it is necessary to set T0 up as a free running timer which is stopped by the active low bus driver...

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Page 19: ...lti Inter PCB Conn Multi Inter PCB Conn Multi Inter PCB Conn Multi Inter PCB Conn Multi Inter PCB Conn Terminals Test Lead Fastening Rivet Socket IC TH Misc XTAL Th Module CAP SM TANT CAP SM TANT CAP SM TANT IC Interface SM Periph IC Interface SM Periph IC Interface SM Periph IC Processor Th STD IC STD Logic SM TTL IC STD Logic SM TTL IC STD Logic SM HCT Inductor SM Misc Inductor SM Misc RES Fixed...

Page 20: ...19 20 21 22 23 24 25 26 27 28 29 30 31 32 gnd o o gnd 5V o o 5V D0 o o D1 D2 o o D3 D4 o o D5 D6 o o D7 A0 o o gnd A2 o o A1 A4 o o A3 A6 o o A5 A8 o o A7 A10 o o A9 A12 o o A11 A14 o o A13 A16 o o A15 A18 o o A17 CM0 o o A19 CM2 o o CM1 ADRSTB o o gnd DATACK o o DATSTB TRFERR o o gnd ATNRQ0 o o SYSRST ATNRQ2 o o ATNRQ1 ATNRQ4 o o ATNRQ3 ATNRQ6 o o ATNRQ5 gnd o o ATNRQ7 BUSRQ0 o o BUSRQ1 BUSAK0 o ...

Page 21: ...O connector 10 way ribbon cable Page 21 J90 SC88T 2192 08819 000 000 channel B data in channel B CTS in gnd channel A RTS out channel A data out channel B data out channel B RTS out n c channel A CTS in 2 channel A data in 9 7 5 3 1 10 8 6 4 2 o o o o o o o o o o ...

Page 22: ...ximum 128k EPROM maximum supplied with 4k RAM Off board memory 1MB via STEbus on board I O 2 DMA controllers 3 counter timers Zilog 8530 SCC Two RS232 channels with optional handshaking Off board I O 4096 locations via STEbus Bus STEbus Bus connector 64 a c DIN41612 Format Single Eurocard Dimensions 167mm x 100mm x 12mm Weight 160g J90 SC88T Page 22 2192 08819 000 000 ...

Page 23: ...Appendix D Example Programs Page 23 J90 SC88T 2192 08819 000 000 ...

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Page 30: ...Appendix E Circuit Diagrams J90 SC88T Page 30 2192 08819 000 000 ...

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