Arcom SC88T, Technical Manual

Page: 14 / 34

Internal block control register map
After a reset, the 256-byte Internal Control Block base address will be at FF00
(Hex) in I/O space. The individual control registers reside within the block, at
fixed-offsets from the base address. Each register is 16-bits wide.
Note that programming the control block is not a trivial task. More detailed
information on how to do this may be found in the Intel 80188 data book. This
manual covers values for most useful memory maps for the SC88T.
If PACS is loaded with OFBE and MPCS is loaded with 80B8 then the Peripheral
Chip Select map appears as below.
J90 SC88T
Page 14
2192-08819-000-000
Base +offset
FF00 +20 to +3E
+50 to +56
+58 to +5E
+60 to +66
+A0
+A2
+A4
+A6
+A8
+C0 to +CA
+D0 to +DA
+FE
UMCS
LMCS
PACS
MMCS
MPCS
Interrupt Controller
Timer 0 Control
Timer 1 Control
Timer 2 Control
Upper Memory Chip Select
Lower Memory Chip Select
Peripheral Base Address Control
Middle Memory Chip Select
Middle Peripheral Chip Select
DMA Descriptors Channel 0
DMA Descriptors Channel 1
Relocation register
Control Block register
Base +offset
F800 +000
+080
081
082
083
+100
+180
+200
+280
+300
+380
PCS0
PCS1
PCS2
PCS3
PCS4
PCS5
PCS6
PCS7
not used
SCC channel B control
SCC channel A control
SCC channel B data
SCC channel A data
Read to generate INTA* and fetch vector
from the SCC (i.e. the interrupt acknowledge
address)
Writing a byte with D0 = 1 asserts /ATOUT
(low) Do not read, as D0 will not be
predictable.
not used
not used
not used
not used
Peripheral Chip Select I/O map