Arcom SC88T, Technical Manual

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Section 3. STEbus Interface
The SC8TT has a STEbus interface with the IEEE number P1000. Here is a
summary of the features of the bus with some notes on their implementation on
the SC88T board. The pinout of the bus is given in Appendix B.
Table 1. STEbus interface on the SC88T
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J90 SC88T 2192-08819-000-000
Signal
A0 - A19
A0 - 11
A0 - 2
D0 - 7
ADRSTB*
DATSTB*
CM2
CM1
CM0
0
0
0
I/O
0
0
0
0
0
3s
3s
3s
3s
3s
3s
3s
3s
3s
20-bit memory
address
12-bit I/O address
3-bit acknowledge
address
8-bit data bus
Address Strobe
Data Strobe
Buffered from the CPU 20-bit address.
As above.
The SC88T does not handle bus-vectored
interrupts, so it does not generate
acknowledge cycles. It does respond to bus
non-vectored interrupts on lines ATNRQ0*-
ATNRQ3* if they have been appropriately
jumpered.
Driven by the CPU on write cycles, or by the
slave on read cycles.
Addresses, data and command modifiers are
valid before the falling edge of ADRSTB* and
DATSTB*. Both strobes are active at the same
time on the SC88T.
On the write cycle, valid data and CM0 are
present before this is asserted. On a read
cycle, CM0 height is present before it is
asserted and DATSTB* then indicates to the
slave that the CPU is ready to accept
Command modifiers indicating the type of
bus cycle, according to the following table:
CM 2 1 0
0 0 0 \
0 0 1 } reserved
0 1 0 /
0 1 1 acknowledge
1 0 0 I/O write
1 0 1 I/O read
1 1 0 memory write
1 1 1 memory read
(Note: the acknowledge cycle is NOT
generated by the SC88T.)
In-Out Type Description Implementation