Preliminary - Information Subject to Change - 9/24/98
5 - 20
EZ-USB Development Board
RES#
OUT
Buffered output from RESET button
PA[7..0]
IO
EZ-USB IO port A
PB[7..0]
IO
EZ-USB IO port B
PC[7..0]
IO
EZ-USB IO port C
CLK24
OUT
24 MHz, 50% duty cycle clock (8051 clock)
SCL
OD
Open-drain I
2
C
clock, pulled up to 3.3V with 2.2K resistor on EZDB
SDA
OD
Open-drain I2C data, pulled up to 3.3V with 2.2K resistor on EZDB
Table 5-12: Expansion Connectors Signal Descriptions
Signal
Type
Description
