Analog Devices Lite ADSP-BF527 EZ-KIT, Manual

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ADSP-BF527 EZ-KIT Lite Evaluation System Manual 2-3
ADSP-BF527 EZ-KIT Lite Hardware Reference
The core voltage and clock rate can be set on the fly by the processor. The
input clock is 25 MHz. A 32.768 kHz crystal supplies the real-time clock
(RTC) inputs of the processor. The default boot mode for the processor is
external parallel flash boot. See
“Boot Mode Select Switch (SW2)” on
page 2-11 for information on how to change the default boot mode.
Programmable Flags
The processor has 50 general-purpose input/output (GPIO) signals spread
across four ports (
PF
,
PG
,
PH
, and
PJ
). The pins are multi-functional and
depend on the ADSP-BF527 processor setup. The following tables show
how the programmable flag pins are used on the EZ-KIT Lite.
•
PF
programmable flag pins – Table 2-1
•
PG
programmable flag pins – Table 2-2
•
PH
programmable flag pins – Table 2-3
•
PJ
programmable flag pins – Table 2-4
Table 2-1. PF Port Programmable Flag Connections
Processor Pin Other Processor Function EZ-KIT Lite Function
PF0 PPID0/DR0PRI/ND_D0A
Default: LCD via
U31
buffer.
Expansion interface
J1.72
, PPI connector
P8.8
.
PF1 PPID1/RFS0/ND_D1A
Default: LCD via
U31
buffer.
Expansion interface
J1.73
, PPI connector
P8.9
.
PF2 PPID2/RSCLK0/ND_D2
Default: LCD via
U31
buffer.
Expansion interface
J1.74
, PPI connector
P8.10
.
PF3 PPID3/DT0PRI/ND_D3A
Default: LCD via
U31
buffer.
Expansion interface
J1.75
, PPI connector
P8.11
.
PF4 PPID4/TFS0/ND_D4A/TAC
LK0
Default: LCD via
U31
buffer.
Expansion interface
J2.43
, PPI connector
P8.12
.
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