PPI Interface
1-14
ADSP-BF527 EZ-KIT Lite Evaluation System Manual
By default, the audio codec is setup to use the
SPISEL5
signal as the SPI
chip select when configuring the codec. The chip select is shared with the
HOSTD9
signal. For more information, refer to see
.
PPI Interface
The ADSP-BF527 processor provides a parallel peripheral interface (PPI),
supporting data widths up to 16 bits. The PPI interface provides three
multiplexed frame syncs, a dedicated clock input, and 16 data lines. The
EZ-KIT Lite uses an eight-bit data connection to the TFT LCD module.
The full PPI port is accessible on the PPI connector
P8
and expansion
interface.
The PPI interface can be disconnected from the LCD module by remov-
ing jumper on
JP2
. The
JP2
jumper enables the
U31
and
U32
buffer ICs.
For more information on the LCD module, refer to
. For information on how to enable the PPI connection
to the LCD module, see
“LCD PPI Jumper (JP2)” on page 2-21
.
The PPI signals connect to multi-function pins; the upper eight data bit
signals are configured for the rotary, SPI,
UART1
, and
LED0
interfaces. See
“Touchscreen and Keypad Interface” on page 1-16
for more information.
The PPI interface has a dedicated clock, generated from an on-board oscil-
lator (default) or the expansion interface. The source of the PPI clock can
be configured by software via the
PPI_SEL
signal. The signal connects to
the processor’s flag pin
PG12
by setting
SW13
position 4
ON
. Flag pin
PG12
is
shared with the
HOSTACK_LED2
signal. When the clock select line is used,
HOSTACK
and
LED2
are not available. The
PPISEL
signal does not need to be
driven if the default on-board oscillator is used;
PPISEL
is driven when the
expansion interface is used as the clocking source. Refer to
for more information.
www.BDTIC.com/ADI
Summary of Contents for Lite ADSP-BF527 EZ-KIT
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