Analog Devices Lite ADSP-BF527 EZ-KIT, Manual

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INDEX
I-2 ADSP-BF527 EZ-KIT Lite Evaluation System Manual
D
debugger interface (ZJ1), 1-5
default configuration, of this EZ-KIT Lite, 1-4
design reference info, 1-27
DIP switch (SW13), 1-21 , 1-23 , 2-16 , 2-18
down signal (CDG), 1-17
E
EBIU_DDRCTL0-2 registers, 1-10
ERXD1_HOSTD8 signal, 1-13
ERXD1 signal, 2-19
Ethernet
interface, xiv , 1-18
connector (J9), 1-18 , 2-28
enable switch (SW1), 1-18 , 2-9
LEDs (LED6-7), 2-24
mode switch (SW9), 1-18 , 2-15
PHY IC (U14), 1-12
example programs, 1-26
expansion interface, 1-12 , 1-13 , 1-14 , 1-17 ,
1-24 , 2-13 , 2-15 , 2-21 , 2-26
external memory, 1-7 , 1-9
F
features, of this EZ-KIT Lite, xiii
FET switch (U28), 1-20
flag pins, See programmable flags by name (PFx,
PGs, PHx, PJx)
flash memory
See also parallel flash memory
enable switch (SW7), 2-13
G
general-purpose IO pins, 1-23 , 2-10 , 2-15 ,
2-16 , 2-18 , 2-24
H
Help, online, xxii
HOSTACK_LED2 signal, 1-14
HOSTACK signal, 1-23
HOSTADDR signal, 1-21 , 1-23
HOSTCE signals, 1-19
HOSTD8 signal, 2-19
HOSTD9 signal, 1-14
host interface connector (P13), 1-12 , 2-32
HOSTWR signals, 1-23
HWAIT
enable jumper (JP1), 2-20
port, 1-21 , 1-23
I
installation, of this EZ-KIT Lite, 1-4 , 1-5
IO voltage, 2-2
J
JTAG
interface, 1-24
connector (ZP4), 1-24 , 2-33
CPLD connector (P17), 2-32
jumpers
diagram of locations, 2-20
JP1 (HWAIT enable), 2-20
JP2 (LCD/PPI connect), 1-15 , 2-21
JP3 (STAMP enable), 2-21
JP5 (UART1 loopback), 1-21 , 2-21 , 2-22
JP6 (mic select), 1-20 , 2-22
P14 (VDDINT power), 1-25 , 2-22
P15 (VDDEXT power), 1-25 , 2-22
P16 (VDDDDR power), 1-25 , 2-23
K
key interrupt (KEYIRQ#) signal, 1-16
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