Analog Devices Lite ADSP-BF527 EZ-KIT, Manual

Page: 35 / 117

ADSP-BF527 EZ-KIT Lite Evaluation System Manual 1-11
Using ADSP-BF527 EZ-KIT Lite
Table 1-4 shows the configuration for the PLL registers using a 400 MHz
CCLK
and 133 MHz
SCLK
. The
PLL_CTL
and
PLL_DIV
registers are initial-
ized in the user code to achieve maximum performance.
An example program is included in the EZ-KIT Lite installation directory
to demonstrate how to setup and access the SDRAM interface. For more
information on how to initialize the registers after a reset, search the Visu-
alDSP++ online Help for “reset values”.
Parallel Flash Memory Interface
The parallel flash memory interface of the ADSP-BF527 EZ-KIT Lite
contains a 4 MB (2M x 16 bits) ST Micro M29W320EB chip. Flash
memory connects to the 16-bit data bus and address lines 1 through 19.
Chip enable is decoded by using
AMS0–3
select lines through NAND and
AND gates. The address range for flash memory is
0x2000 0000
to
0x203F FFFF
.
Flash memory is pre-loaded with boot code for the blink, LCD images,
and power-on-self test (POST) programs. For more information, refer to
“Power-On-Self Test” on page 1-25 .
By default, the EZ-KIT Lite boots from the 16-bit parallel flash memory.
The processor boots from flash memory if the boot mode select switch
(
SW2
) is set to a position of 1 (see “Boot Mode Select Switch (SW2)” on
page 2-11 ).
Table 1-4. PLL Register Settings
Register SCLK = 133 MHz
CCLK = 400 MHz
PLL_CTL 16
PLL_DIV 3
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