Analog Devices Lite ADSP-BF527 EZ-KIT, Manual

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ADSP-BF527 EZ-KIT Lite Evaluation System Manual 2-7
ADSP-BF527 EZ-KIT Lite Hardware Reference
PG13 DMAR0/UART1RXA/HOST_
ADDR/TACI2
Default:
PB2
via
SW13.2
.
OTG
USB_VRSEL
via
SW13.6 ON
and
SW13.2 OFF
, host
connector
P13.8
, and expansion interface
J1.85
.
PG14 TSCLK0A/MDC/HOST_RD#
Default: host connector
P13.2.13.6
MDIO
PHY (
U14
) via
SW1.2
, expansion interface
J3.41
PG15 TFS0A/MIIPHY-
INT#/RMIIM-
DINT#/HOST_CE#
Default: SPORT0 audio codec (
U2
) via
SW20.1
RMIIMDINT#
PHY (
U14
), host connector
P13.6
,
SPORT0 connector
P6.11
, and expansion interface
J2.40
,
J3.31
.
Table 2-3. PH Port Programmable Flag Connections
Processor Pin Other Processor Function EZ-KIT Lite Function
PH0 ND_D0/MIICRS/RMII-
CRSDV/HOST_D0
Default: NAND Data 0 (
U4
).
RMII carrier sense/receive data valid (
U14.36
), host
connector data 0 (
P13.31
), and expansion interface
(
J3.40
).
PH1 ND_D1/ERXER/HOST_D1
Default: NAND Data 1 (
U4
).
PHY receive error (
U14.21
), host connector data 1
(
P13.29
), expansion interface (
J3.39
).
PH2 ND_D2/MDIO/HOST_D2
Default: NAND Data 2 (
U4
).
PHY management bus
MDIO
via
SW1.1
, host connector
data 2 (
P13.27
), and expansion interface (
J3.42
).
PH3 ND_D3/ETXEN/HOST_D3
Default: NAND Data 3 (
U4
).
PHY transmit enable (
U14.6
), host connector data 3
(
P13.25
), and expansion interface (
J3.15
).
PH4 ND_D4/MIITX-
CLK/RMIIREF_CLK/HOST_
D4
Default: NAND Data 4 (
U4
).
PHY RMII ref clock (
U14.14
) via
SW1.3 OFF
, oscillator
output
U24
, host connector data 4 (
P13.23
), and
expansion interface (
J3.16
).
PH5 ND_D5/ETXD0/HOST_D5
Default: NAND Data 5 (
U4
).
PHY RMII transmit data 0 (
U14.23
), host connector
data 5 (
P13.21
), and expansion interface (
J3.11
).
Table 2-2. PG Port Programmable Flag Connections (Cont’d)
Processor Pin Other Processor Function EZ-KIT Lite Function
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