Evaluation Board User Guide
UG-046
Rev. 0 | Page 5 of 32
CONFIGURING THE PLL FILTER
The PLL for the
AD1974
can run from either MCLK or LRCLK,
according to its setting in the PLL and Clock Control 0 register,
Bits[6:5]. The matching RC loop filter must be connected to LF
(Pin 47) using JP15. See Figure 11 and Figure 12 for the jumper
positions.
08424-
011
C
114
C120
C131
JP15
M
CL
K
L
RCL
K
R129
C125
R138
PLL SELECT
Figure 11. MCLK Loop Filter Selected
08424-
012
C
114
C120
C131
JP15
M
CL
K
L
RCL
K
R129
C125
R138
PLL SELECT
Figure 12. LRCLK Loop Filter Selected
Normally, the MCLK filter is the default selection; it is also
possible to use the register control window to program the PLL
to run from the LRCLK. In this case, the jumper must be
changed as shown in Figure 12.
CONNECTING AUDIO CABLES
Analog Audio
The analog inputs and outputs use 3.5 mm TRS jacks; they are
configured in the standard configuration: tip = left, ring = right,
sleeve = ground. The analog inputs to IN1 and IN2 generate
0 dBFS from a 1 V rms analog signal. The on-board buffer
circuit creates the differential signal to drive the ADC with 2 V
rms at the maximum level. There are test points that allow
direct access to the ADC pins; note that the ADC pins have a
common mode voltage of 1.5 V dc. These test points require
proper care so that improper loading does not drag down the
common-mode voltage, and the headroom and performance of
the part do not suffer.
The ADC buffer circuit has been designed with a switch (S1)
that allows the user to change the voltage reference for all of the
amplifiers. GND, CM and FILTR can be selected as a reference;
it is advisable to shut down the power to the board before
changing this switch. The CM and FILTR lines are very
sensitive and do not react well to a change in load while the
AD1974 is active. A series of jumpers allows the user to dc-
couple the buffer circuit to the ADC analog port in when CM
and FILTR are selected (see Figure 13).
08424-
013
R72
C60
R73
S1
C74
C63
C61
C64
C65
C67
C69
R84
R86
C76
C99
R106
R107
U14
C77
C82
C80
C83
C88
R85
R87
TP32
TP28
VREF SELECT
TP26
IN1R+
IN1R–
IN1L+
IN1L–
TP34
R
79R
77C
62
C6
6
C7
9
R9
7
R9
3
JP
12
R9
0
C8
9
R7
6
G
ND
FI
LTE
R
CM
J
P4
C6
8
C7
2
JP
11
R8
1
R
101
JP
13
C
105
C7
5
U12
TP25
IN1L
IN1R
TP30
Figure 13. VREF
S
election and DC Coupling Jumpers
Digital Audio
There are two types of digital interfacing, S/PDIF and discrete
serial. The S/PDIF transmitter port has both optical and coaxial
connectors that can be used simultaneously. The serial audio
connectors use 1 × 2 100 mil spaced headers, signal and ground.
The LRCLK, BCLK, and SDATA paths are available for the
ADC on the HDR1 and HDR2 connectors. Each has a
connection for MCLK; each HDR MCLK interface has a switch
to set the port as an input or output, depending on the
configuration of the evaluation board.
SWITCH AND JUMPER SETTINGS
Clock and Control
The AD1974 is designed to run in standalone mode at a sample
rate (f
S
).of 48 kHz, with an MCLK of 12.288 MHz (256 × f
S
). In
standalone slave mode, the ADC port must receive valid BCLK
and LRCLK. The AD1974 can be clocked from the HDR1 con-
nector; the ADC BCLK and LRCK port sources are selected
with S2, Position 2 and Position 3. For HDR1 as master, S2,
Position 3, should be on (see the detail in Figure 14 and Figure 15).
Note that HDR2 is not implemented in the CPLD routing code.
It is also possible to configure the AD1974 ADC BCLK and
LRCK ports to run in standalone master mode; moving J5 to
SDA/1, as shown in Figure 3, changes the state of the AD1974.
Setting S2, Position 2, to on selects the proper routing to both
the S/PDIF transmitter and the HDR1 connector. In this mode,
the AD1974 ADC port generates BCLK and LRCLK when given
a valid MCLK.
For the full flexibility of the AD1974, the part can be put in SPI
control mode and programmed with the
Automated Register
Window Builder
application (see Figure 4 for the appropriate
jumper settings). Changing the registers and setting the DIP
switches allow many possible configurations. In the various
master and slave modes, the AD1974 takes MCLK from a
selected source and can be set to generate or receive either
BCLK or LRCLK to or from either the ADC or the DAC port,
depending on the settings and requirements.
