UG-046
Evaluation Board User Guide
Rev. 0 | Page 6 of 32
As an example, to set the ADC port as master, switch the ADC
Control Register 2 bits for BCLK and LRCLK to master and
change S2, Position 2, and S2, Position 5, to on. In this mode,
the board is configured so that the ADC BCLK and LRCLK
pins are the clock source for both the ADC destination and the
DAC data source. For the DAC port to be the master, the DAC
Control Register 1 bits for BCLK and LRCLK must be changed
to master, and S2, Position 2 and Position 3, and S2, Position 5
and Position 6, must all be on. On this evaluation board, these
settings allow the master port on the
AD1974
to drive both the
S/PDIF and the HDR connections. Many combinations of
master and slave are possible (see Figure 14 and Figure 15 for
the correct settings).
S/PDIF Audio
The settings in Figure 14 and Figure 15 show the details of clock
routing and control for the ADC port. The board is shipped
with the IN1 analog port selected as default feed to the S/PDIF
transmitter; the hex switches are set to 0 and only the S2,
Position 2, DIP switch is on. All other switches are set to off.
The evaluation board is shipped in standalone master mode
(see Figure 3); the BCLK and LRCLK signals run from the ADC
port of the AD1974 to the S/PDIF transmitter and HDR1.
In this default configuration, IN1 analog is routed through the
AD1974 ADC ASDATA1 path to the S/PDIF output. By changing
DIP switch S3, Position 8, from 0 to 1, IN2 is selected.
HDR Connectors—Serial Audio
Routing of serial audio to the HDR1 connector is controlled by
DIP S3, Position 6 and Position 7. The default condition routes
IN1 to ASDATA1 and IN2 to ASDATA2.
Other Options
To use other f
S
rates, the USBi must be connected and the AD1974
registers must be programmed accordingly. For example,
adjusting the f
S
rate to 96 kHz requires that the ADC Control 0
register have the sample rate set to 96 kHz (see Figure 14 and
Figure 15 for the complete list of options).
The CPLD code is presented in the CPLD Code section and is
included with the evaluation board; alterations and additions to
the functionality of the CPLD are possible by altering the code
and reprogramming the CPLD.
