UG-046
Evaluation Board User Guide
Rev. 0 | Page 4 of 32
08424-
005
JP5
A
V
DD2
A
V
DD1
DV
DD
JP6
JP7
POWER SELECTION
Figure 5. AD1974 Power Jumpers
SETTING UP THE MASTER CLOCK (MCLK)
The
AD1974
evaluation board has a series of jumpers that give
the user great flexibility in the MCLK clock source for the
AD1974. MCLK can come from five sources: passive crystal,
active oscillator, external clock in, and two header connections.
Note that the CPLD on the board must have a valid clock
source; the frequency is not critical. These jumper blocks can
assign this CPLD clock. Most applications of the board use
MCLK from either the oscillator or one of the header (HDR)
inputs. Figure 6 to Figure 7 show the on-board active oscillator
disabled so that it does not interfere with the selected clock. The
clock feed to the CPLD comes directly from the clock source.
Note that, if the HDR connectors are to be driven with MCLK
from a source on the evaluation board, SW2 and/or SW3 must
be switched from the IN position to the OUT position.
08424-
006
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP
24
O
SC
R
155
R
156
C
154
C
153
M
CL
KI
X
T
AL
MCLKO
XTAL
R
166
R
178
M
CL
KI
BUS
M
CL
KO
BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18
JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 6. Active On-Board Oscillator as Master; the AD1974 and
CPLD as Slaves
08424-
007
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP
24
O
SC
R
155
R
156
C
154
C
153
M
CL
KI
X
T
AL
MCLKO
XTAL
R
166
R
178
M
CL
KI
BUS
M
CL
KO
BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18
JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 7. HDR1 as MCLK Master; the AD1974, CPLD, and HDR2 as Slaves
08424-
008
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP
24
O
SC
R
155
R
156
C
154
C
153
M
CL
KI
X
T
AL
MCLKO
XTAL
R
166
R
178
M
CL
KI
BUS
M
CL
KO
BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18
JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 8. External Clock In as Master; the AD1974 and CPLD as Slaves
The MCLK configurations shown in Figure 9 and Figure 10 use
the AD1974 MCLKO port to drive the CPLD and, possibly, the
HDRs. The passive crystal runs the AD1974 at 12.288 MHz.
Figure 10 shows the MCLKI shut off; this is the case when the
PLL is set to LRCLK instead of to MCLK.
08424-
009
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP
24
O
SC
R
155
R
156
C
154
C
153
M
CL
KI
X
T
AL
MCLKO
XTAL
R
166
R
178
M
CL
KI
BUS
M
CL
KO
BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18
JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 9. Passive Crystal; the AD1974 Is Master; the CPLD Is Slave from
the MCLKO Port
08424-
010
JP31
HDR1
JP30
HDR2
JP29
8416
JP28
CLK
JP
24
O
SC
R
155
R
156
C
154
C
153
M
CL
KI
X
T
AL
MCLKO
XTAL
R
166
R
178
M
CL
KI
BUS
M
CL
KO
BUS
JP27
HDR1
JP25
HDR2
JP23
CPLD
OSC DISABLE
193X_MCLKI
DISABLE
EXT
EXT CLK IN
193X_MCLKO
1938_MCLKI
R160
R167
R169
R172
R174
R175
C168
C170
JP22
C158
L7
JP19
JP18
JP20
C147
U21
U18
U22
Y1
J23
J22
Figure 10. LRCLK Is the Master Clock Using the PLL; MCLKI Is Disabled
,
and
CPLD Is Slave to the MCLKO Port
