UG-046
Evaluation Board User Guide
Rev. 0 | Page 24 of 32
// M3_8414 = 0;
// CS8404 Tx interface mode select
APMS_TX = 0; // Tx serial port is always slave in this application
SFMT1_TX = 0; // Tx data format is I2S always
SFMT0_TX = 1;
// M0_8404 = 0;
// M1_8404 = 0;
// M2_8404 = 1; // I2S format only
// divide 256Fs clock by 2 for 128Fs clock to the the S/PDIF Tx
// Qdivide.clk = CPLD_MCLK;
// Qdivide.d = !Qdivide;
// MCLK_8406 = Qdivide;
MCLK_8406 = CPLD_MCLK;
BCLK_8406 = I_ABCLK;
LRCLK_8406 = I_ALRCLK;
SDATA_8406 = (ASDATA1 & S/PDIF_OUT_MUX) # (ASDATA2 & !S/PDIF_OUT_MUX);
// For SPI mode, let external port drive the SPI port
DBCLK.oe = (DAC_S/PDIF # DAC_HDR1 # DAC_ADC # !DAC_DAC) & (DAC_CLK_OFF);
DLRCLK.oe = (DAC_S/PDIF # DAC_HDR1 # DAC_ADC # !DAC_DAC) & (DAC_CLK_OFF);
ABCLK.oe = (ADC_S/PDIF # ADC_HDR1 # !ADC_ADC # ADC_DAC) & (ADC_CLK_OFF);
ALRCLK.oe = (ADC_S/PDIF # ADC_HDR1 # !ADC_ADC # ADC_DAC) & (ADC_CLK_OFF);
HDR1_DBCLK.oe = (DAC_S/PDIF # !DAC_HDR1 # DAC_ADC # DAC_DAC);
HDR1_DLRCLK.oe = (DAC_S/PDIF # !DAC_HDR1 # DAC_ADC # DAC_DAC);
HDR1_ABCLK.oe = (ADC_S/PDIF # !ADC_HDR1 # ADC_ADC # ADC_DAC);
HDR1_ALRCLK.oe = (ADC_S/PDIF # !ADC_HDR1 # ADC_ADC # ADC_DAC);
BCLK_8416.oe = (!DAC_S/PDIF);
LRCLK_8416.oe = (!DAC_S/PDIF);
BCLK_8416 = I_DBCLK;
LRCLK_8416 = I_DLRCLK;
DSDATA1.oe = (!DAC_DATA_HIZ);
DSDATA2.oe = (!(DAC_HDR1_TDM # DAC_DUAL_TDM # DAC_DATA_HIZ)); //DSDATA2 is output in DAC
TDM-daisy chain mode
DSDATA3.oe = (!DAC_DATA_HIZ);
DSDATA4.oe = (!(DAC_DUAL_TDM # ADC_HDR_AUX # DAC_HDR1_AUX # DAC_DATA_HIZ)); // SECOND
TDM-OUT IN DUAL LINE DAC TDM MODE
ASDATA2.oe = (ADC_HDR_TDM); //ASDATA2 is input in ADC TDM mode
HDR1_DSDATA2.oe = (DAC_HDR1_TDM # DAC_DUAL_TDM);
