Analog Devices ADM1026 Preliminary Technical Data Download Page 8

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ADM1026

PRELIMINARY TECHNICAL DATA

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REV. PrL

PRELIMINAR

TECHNICAL

the volatile registers. Although referred to as Read Only
Memory, the EEPROM can be written to (as well as read
from) via the serial bus in exactly the same way as the
other registers. The only major differences between the
E

PROM and other registers are:

1. An EEPROM location must be blank before it can be

written to. If it contains data, it must first be erased.

2. Writing to EEPROM is slower than writing to RAM.

3. Writing to the EEPROM should be restricted because

it has a limited write/cycle life of typically 10,000 write
operations, due to the usual EEPROM wear-out
mechanisms.

SERIAL BUS INTERFACE

Control of the ADM1026 is carried out via the serial Sys-
tem Management Bus (SMBus). The ADM1026 is con-
nected to this bus as a slave device, under the control of a
master device.

The ADM1026 has a 7-bit serial bus slave address. When
the device is powered up, it will do so with a default serial
bus address. The five MSB's of the address are set to
01011, the two LSB's are determined by the logical states
of pin 15 (ADD/NTESTOUT). This is a three-state in-
put that can be grounded, connected to V

or left open-

circuit to give three different addresses.

TABLE 1. ADDRESS PIN TRUTH TABLE

ADD Pin

G N D

No Connect

If ADD is left open-circuit the default address will be
0101110. ADD is sampled only at power-up, so any changes
made while power is on will have no immediate effect.

The facility to make hardwired changes to A1 and A0 al-
lows the user to avoid conflicts with other devices sharing
the same serial bus, for example if more than one
ADM1026 is used in a system.

GENERAL SMBUS TIMING

Figures 2a and 2b show timing diagrams for general read
and write operations using the SMBus. The SMBus speci-
fication defines specific conditions for different types of
read and write operation, which are discussed later.

The general SMBus protocol operates as follows:

1. The master initiates data transfer by establishing a

START condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line
SCL remains high. This indicates that an data stream
will follow. All slave peripherals connected to the serial
bus respond to the START condition, and shift in the
next 8 bits, consisting of a 7-bit slave address (MSB
first) plus a R/

bit, which determines the direction of

the data transfer, i.e. whether data will be written to or
read from the slave device (0 = write, 1 = read).

The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit, and holding it low dur-
ing the high period of this clock pulse. All other de-
vices on the bus now remain idle whilst the selected
device waits for data to be read from or written to it. If
the R/

bit is a 0 then the master will write to the slave

device. If the R/

bit is a 1 the master will read from

the slave device.

2. Data is sent over the serial bus in sequences of 9 clock

pulses, 8 bits of data followed by an Acknowledge Bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal
and remain stable during the high period, as a low to
high transition when the clock is high may be inter-
preted as a STOP signal.

If the operation is a write operation, the first data byte
after the slave address is a command byte. This tells the
slave device what to expect next. It may be an instruc-
tion such as telling the slave device to expect a block
write, or it may simply be a register address that tells
the slave where subsequent data is to be written.

R / W

S C L

S D A

D 7

D 6

D 5

D 4

D 3

D 2

D 1

D 0

ACK. BY