ADM1026
PRELIMINARY TECHNICAL DATA
– 1 0 –
REV. PrL
PRELIMINAR
Y
TECHNICAL
DA
TA
ADM1026 WRITE OPERATIONS
The SMbus specification defines several protocols for dif-
ferent types of read and write operations. The ones used in
the ADM1026 are discussed below. The following abbre-
viations are used in the diagrams:
S
-
START
P
-
S T O P
R
-
READ
W
-
WRITE
A
-
A C K N O W L E D G E
A
-
NO ACKNOWLEDGE
The ADM1026 uses the following SMBus write protocols.
Send Byte
In this operation the master device sends a single com-
mand byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a STOP condition on SDA and the
transaction ends.
In the ADM1026, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read
from the same address or block read or write starting at
that address. This is illustrated in Figure 3a.
S
S LAV E
ADDRE S S
W
A
RAM
ADDRE S S
(00h TO 6Fh)
A P
1
2
3
4
5
6
Figure 3a. Setting A RAM Address For Subsequent Read
If it is required to read data from the RAM immediately
after setting up the address, the master can assert a repeat
start condition immediately after the final ACK and carry
out a single byte read, block read or block write opera-
tion, without asserting an intermediate stop condition.
Write Byte/Word
In this operation the master device sends a command byte
and one or two data bytes to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master sends a data byte (or may assert STOP at
this point).
9. The slave asserts ACK on SDA.
10.The master asserts a STOP condition on SDA to end
the transaction.
In the ADM1026, the write byte/word protocol is used for
four purposes. The ADM1026 knows how to respond by
the value of the command byte and EEPROM register 3.
1. Write a single byte of data to RAM. In this case the
command byte is the RAM address from 00h to 6Fh
and the (only) data byte is the actual data. This is il-
lustrated in Figure 3b.
S
S L AV E
AD DR E S S
W
A
RA M
AD DR E S S
(00h T O 6F h )
A DA T A
A
P
1
2
3
4
5
6
7
8
Figure 3b. Single Byte Write To RAM
2. Set up a two byte EEPROM address for a subsequent
read or block read. In this case the command byte is
the high byte of the EEPROM address from 80h to
9Fh. The (only) data byte is the low byte of the
EEPROM address. This is illustrated in Figure 3c.
S
S L AV E
AD DR E S S
W
A
E E P RO M
AD DR E S S
HIG H BY T E
(80h T O 9F h )
E E P RO M
AD DR E S S
L O W BY T E
(00h T O F F h )
A
A P
1
2
3
4
5
6
7
8
Figure 3c. Setting An EEPROM Address
If it is required to read data from the EEPROM imme-
diately after setting up the address, the master can as-
sert a repeat start condition immediately after the final
ACK and carry out a single byte read, block read or
block write operation, without asserting an intermedi-
ate stop condition. In this case bit 0 of EEPROM Reg-
ister 3 should be set.
3. Erase a page of EEPROM memory. EEPROM
memory can be written to only if it is unprogrammed.
Before writing to one or more EEPROM memory lo-
cations that are already programmed, the page or pages
containing those locations must first be erased.
EEPROM memory is erased by writing an EEPROM
page address plus an arbitrary byte of data with bit 2 of
EEPROM Register 3 set to 1.
As the EEPROM consists of 128 pages of 64 bytes, the
EEPROM page address consists of the EEPROM ad-
dress high byte (from 80h to 9Fh) and the two MSB's
of the low byte. The lower 6 bits of the EEPROM ad-
dress low byte only specificy addresses within a page
and are ignored during an erase operation.
S
S L AV E
AD DR E S S
W
A
E E P RO M
AD DR E S S
HIG H BY T E
(80h TO 9Fh )
E E P RO M
AD DR E S S
L O W BY T E
(00h TO F F h)
A
A
AR BIT RA RY
DA T A
A P
1
2
3
4
5
6
7
8
9 10
Figure 3d. EEPROM Page Erasure
Page erasure takes approximately 20ms. If the
EEPROM is accessed before erasure is complete, it
will respond with No Acknowledge.
4. Write a single byte of data to EEPROM. In this case
the command byte is the high byte of the EEPROM
address from 80h to 9Fh. The first data byte is the low
