PRELIMINARY TECHNICAL DATA
ADM1026
– 4 5 –
REV. PrL
PRELIMINAR
Y
TECHNICAL
DA
TA
TABLE 43. REGISTER 24H, STATUS REGISTER 5 (POWER-ON DEFAULT 00H)
Bit
Name
R/W
Description
0
GPIO0 Status = 0
R
When GPIO0 is configured as an input , this bit is set when GPIO0 is
asserted. ("asserted" may be active-high or active-low depending on setting of
bit 1 in GPIO Configuration Register 1).
R / W *
When GPIO0 is configured as an output, setting this bit asserts GPIO0.
("asserted" may be active-high or active-low depending on setting of bit 1 in
GPIO Configuration Register 1).
1
GPIO1 Status = 0
R
When GPIO1 is configured as an input , this bit is set when GPIO1 is
asserted. ("asserted" may be active-high or active-low depending on setting of
bit 3 in GPIO Configuration Register 1).
R / W *
When GPIO1 is configured as an output, setting this bit asserts GPIO1.
("asserted" may be active-high or active-low depending on setting of bit 3 in
GPIO Configuration Register 1).
2
GPIO2 Status = 0
R
When GPIO2 is configured as an input , this bit is set when GPIO2 is
asserted. ("asserted" may be active-high or active-low depending on setting of
bit 5 in GPIO Configuration Register 1).
R / W *
When GPIO2 is configured as an output, setting this bit asserts GPIO2.
("asserted" may be active-high or active-low depending on setting of bit 5 in
GPIO Configuration Register 1).
3
GPIO3 Status = 0
R
When GPIO3 is configured as an input , this bit is set when GPIO3 is
asserted. ("asserted" may be active-high or active-low depending on setting of
bit 7 in GPIO Configuration Register 1).
R / W *
When GPIO3 is configured as an output, setting this bit asserts GPIO3.
("asserted" may be active-high or active-low depending on setting of bit 7 in
GPIO Configuration Register 1).
4
GPIO4 Status = 0
R
When GPIO4 is configured as an input , this bit is set when GPIO4 is
asserted. ("asserted" may be active-high or active-low depending on setting of
bit 1 in GPIO Configuration Register 2).
R / W *
When GPIO4 is configured as an output, setting this bit asserts GPIO4.
("asserted" may be active-high or active-low depending on setting of bit 1 in
GPIO Configuration Register 2).
5
GPIO5 Status = 0
R
When GPIO5 is configured as an input , this bit is set when GPIO5 is
asserted. ("asserted" may be active-high or active-low depending on setting of
bit 3 in GPIO Configuration Register 2).
R / W *
When GPIO5 is configured as an output, setting this bit asserts GPIO5.
("asserted" may be active-high or active-low depending on setting of bit 3 in
GPIO Configuration Register 2).
6
GPIO6 Status = 0
R
When GPIO6 is configured as an input , this bit is set when GPIO6 is
asserted. ("asserted" may be active-high or active-low depending on setting of
bit 5 in GPIO Configuration Register 2).
R / W
When GPIO6 is configured as an output, setting this bit asserts GPIO6.
("asserted" may be active-high or active-low depending on setting of bit 5 in
GPIO Configuration Register 2).
7
GPIO7 Status = 0
R
When GPIO7 is configured as an input , this bit is set when GPIO7 is
asserted. ("asserted" may be active-high or active-low depending on setting of
bit 7 in GPIO Configuration Register 2).
R / W *
When GPIO7 is configured as an output, setting this bit asserts GPIO7.
("asserted" may be active-high or active-low depending on setting of bit 7 in
GPIO Configuration Register 2).
*Note: GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.
