PRELIMINARY TECHNICAL DATA
ADM1026
– 4 1 –
REV. PrL
PRELIMINAR
Y
TECHNICAL
DA
TA
TABLE 34. REGISTER 1BH, MASK REGISTER 4 (POWER-ON DEFAULT 00H)
Bit
Name
R/W
Description
0
Int Temp Mask = 0
R / W
When this bit is set, interrupts generated on the Int Temp channel are masked
out.
1
V
BAT
Mask = 0
R / W
When this bit is set, interrupts generated on the V
BAT
Voltage channel are
masked out.
2
A
IN8
Mask = 0
R / W
When this bit is set, interrupts generated on the A
IN8
Voltage channel are
masked out.
3
THERM Mask = 0
R / W
When this bit is set, interrupts generated from THERM events are masked
out.
4
AFC Mask = 0
R / W
When this bit is set, interrupts generated from Automatic Fan Control events
are masked out.
5
0
R
Unused. Will read back 0.
6
CI Mask = 0
R / W
When this bit is set, interrupts generated by the Chassis Intrusion input are
masked out.
7
GPIO16 Mask = 0
R / W
When this bit is set, interrupts generated on the GPIO16 channel are
masked out.
TABLE 35. REGISTER 1CH, MASK REGISTER 5 (POWER-ON DEFAULT 00H)
Bit
Name
R/W
Description
0
GPIO0 Mask = 0
R / W
When this bit is set, interrupts generated on the GPIO0 channel are masked
out.
1
GPIO1 Mask = 0
R / W
When this bit is set, interrupts generated on the GPIO1 channel are masked
out.
2
GPIO2 Mask = 0
R / W
When this bit is set, interrupts generated on the GPIO2 channel are masked
out.
3
GPIO3 Mask = 0
R / W
When this bit is set, interrupts generated on the GPIO3 channel are masked
out.
4
GPIO4 Mask = 0
R / W
When this bit is set, interrupts generated on the GPIO4 channel are masked
out.
5
GPIO5 Mask = 0
R / W
When this bit is set, interrupts generated on the GPIO5 channel are masked
out.
6
GPIO6 Mask = 0
R / W
When this bit is set, interrupts generated on the GPIO6 channel are masked
out.
7
GPIO7 Mask = 0
R / W
When this bit is set, interrupts generated on the GPIO7 channel are masked
out.
