AMIMON AMN12310 WHDI, Datasheet

Page: 24 / 39

Interfaces
Version 0.5
AMIMON Confidential 24
The following table specifies the timing parameters -
Table 8: Reset Timing Requirements
Symbol Parameter Condition MIN TYP MAX Units
T
RST-CLK
Time from assertion of the HW reset until valid
clock is generated 40 MHz clock is valid –
few us after power up 300 ns
T
ST,RST
Time from assertion of the HW reset until the
STM32F completes the internal initialization
Power is stable 4.5 ms
T
INIT
Time from assertion of the HW/SW reset until the
AMN2210 completes the internal initialization 1.7 ms
The following figure specifies the reset schema and related signals -
Figure 11: Reset Mechanism