AMIMON AMN12310 WHDI, Datasheet

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Interfaces
Version 0.5
AMIMON Confidential 18
3.3.1 I
2
S Bus Specification
The AMN12310 supports a standardized communication structure inter-IC sound (I
2
S) bus. As shown in Figure 5,
the bus has three lines: continuous serial clock (SCK), word select (WS) and serial data (SD). In addition, it has a
MCLK signal which is synchronized to and a multiple of the WS. The external device generating SCK and WS is
the AMN12310.
Figure 5: I
2
S Simple System Configurations and Basic Interface Timing
The AMN12310 outputs exactly 32 bits for each channel (left and right). By default, the serial data is valid on the
leading (LOW to HIGH) edge of the clock signal, but it can also be configured to be valid on the edge (HIGH to
LOW) of the clock signal. The WS is also valid by default on the leading edge of the clock signal. The WS line
changes one clock period before the first bit of the transmitted channel.
The AMN12310 mirrors the transmitter's end audio inputs and so the MSB and the LSB position are defined at
the audio source at the transmitter side. In case the audio samples in the transmitter are less than 32 bits long,
they are padded with zeroes to generate receiver output samples of 32 bits.
3.3.1.1 MUTE
The AMN12310 has an error detection mechanism. It outputs a high MUTE signal in case of bad audio reception
(bad frames).