32
Electrical Data
Chapter 7
AMD Athlon™ XP Processor Model 6 Data Sheet
24309E—March 2002
Preliminary Information
7.10
SYSCLK and SYSCLK# AC and DC Characteristics
Table 9 shows the DC characteristics of the SYSCLK and
SYSCLK# differential clocks. The SYSCLK signal represents
CLKIN and RSTCLK tied together while the SYSCLK# signal
represents CLKIN# and RSTCLK# tied together.
Figure 9 shows the DC characteristics of the SYSCLK and
SYSCLK# signals.
Figure 9. SYSCLK and SYSCLK# Differential Clock Signals
Table 9.
SYSCLK and SYSCLK# DC Characteristics
Symbol
Description
Min
Max
Units
V
Threshold-DC
Crossing before transition is detected (DC)
400
mV
V
Threshold-AC
Crossing before transition is detected (AC)
450
mV
I
LEAK_P
Leakage current through P-channel pullup to VCC_CORE
–250
µA
I
LEAK_N
Leakage current through N-channel pulldown to VSS (Ground)
250
µA
V
CROSS
Differential signal crossover
VCC_CORE/2
±100
mV
C
PIN
Capacitance *
4
12
pF
Note:
*
The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.
SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.
V
CROSS
V
Threshold-DC
= 400mV
V
Threshold-AC
= 450mV