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Pin Descriptions
Chapter 10
AMD Athlon™ XP Processor Model 6 Data Sheet
24309E—March 2002
Preliminary Information
See “NC Pins“ for more information.
NC Pins
The motherboard should provide a plated hole for an NC pin.
The pin hole should not be electrically connected to anything.
NMI Pin
NMI is an input from the system that causes a non-maskable
interrupt.
PGA Orientation Pins
No pin is present at pin locations A1 and AN1. Motherboard
designers should not allow for a PGA socket pin at these
locations.
For more information, see the
AMD Athlon™ Processor-Based
Motherboard Design Guide
, order# 24363.
PLL Bypass and Test
Pins
P L LT E S T # , P L L B Y PA S S # , P L L M O N 1 , P L L M O N 2 ,
PLLBYPASSCLK, and PLLBYPASSCLK# are the PLL bypass
and test interface. This interface is tied disabled on the
motherboard. All six pin signals are routed to the debug
connector. All four processor inputs (PLLTEST#, PLLBYPASS#,
PLLMON1, and PLLMON2) are tied to VCC_CORE with pullup
resistors.
PWROK Pin
The PWROK input to the processor must not be asserted until
all voltage planes in the system are within specification and all
system clocks are running within specification.
For more information, Chapter 8, “Signal and Power-Up
Requirements” on page 43.
SADDIN[1:0]# and
SADDOUT[1:0]# Pins
The AMD Athlon XP processor model 6 does not support
SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC
with pullup resistors, if this bit is not supported by the
Northbridge (future models can support SADDIN[1]#).
SADDOUT[1:0]# are tied to VCC with pullup resistors if these
pins are supported by the Northbridge. For more information,
s e e t h e
A M D A t h l o n ™ a n d A M D D u r o n ™ S y s t e m B u s
Specification
, order# 21902.
Scan Pins
SCANSHIFTEN, SCANCLK1, SCANINTEVAL, and SCANCLK2
are the scan interface. This interface is AMD internal and is
tied disabled with pulldown resistors to ground on the
motherboard.