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Pin Descriptions
Chapter 10
AMD Athlon™ XP Processor Model 6 Data Sheet
24309E—March 2002
Preliminary Information
FID[3:0] Pins
FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the
4-bit processor clock-to-SYSCLK ratio.
Table 21 describes the encodings of the clock multipliers on
FID[3:0].
The FID[3:0] signals are open drain processor outputs that are
pulled High on the motherboard and sampled by the chipset to
determine the SIP (Serialization Initialization Packet) that is
sent to the processor. The FID[3:0] signals are valid after
PWROK is asserted. The FID[3:0]signals must not be sampled
u n t i l t h e y b e c o m e va l i d . S e e t h e
A M D A t h l o n ™ a n d
AMD Duron™ System Bus Specification
, order# 21902 for more
information about Serialization Initialization Packets and SIP
protocol.
Table 21. FID[3:0] Clock Multiplier Encodings
FID[3:0]
2
Processor Clock to SYSCLK Frequency Ratio
0000
11
0001
11.5
0010
12
0011
≥
12.5
1
0100
5
0101
5.5
0110
6
0111
6.5
1000
7
1001
7.5
1010
8
1011
8.5
1100
9
1101
9.5
1110
10
1111
10.5
Notes:
1. All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011, which causes
the SIP configuration for all ratios of 12.5x or greater to be the same.
2. BIOS initializes the CLK_Ctl MSR to 6003_D22Fh during the POST routine. This CLK_Ctl
setting is used with all FID combinations and selects a Halt disconnect divisor of 64 and a Stop
Grant disconnect divisor of 64. For more information, refer to the
AMD Athlon™ and
AMD Duron™ Processors BIOS, Software, and Debug Developers Guide
, order# 21656.