AMD Am186 Series, Instruction Set

Page: 255 / 320

Instruction Set 4-215
SAR SAR
Flag Settings After Instruction
If
count=0, flags are unaffected. Otherwise, flags are affected as shown below:
Examples
This example divides an 8-bit integer in memory by 2.
This example divides a 16-bit integer in DX by 4.
Tips
If the integer dividend will fit in a 16-bit register and you don’t need the remainder, use SAR
to divide integers by powers of 2. When dividing an integer by a power of 2, it is faster to
use SAR than IDIV.
Related Instructions
If you want to See
Divide an unsigned number by another unsigned number DIV
Divide an integer by another integer IDIV
Rotate the bits of a component and the value of CF to the left RCL
Rotate the bits of a component and the value of CF to the right RCR
Rotate the bits of a component to the left ROL
Rotate the bits of a component to the right ROR
Multiply an integer by a power of 2 SAL/SHL
Divide an unsigned number by a power of 2 SHR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Processor Status
Flags Register
reserved
OF DF IF TF SF ZF AF PF CF
? = undefined; – = unchanged
Undefined unless single-bit shift, then:
OF=1 if result larger than destination operand
OF=0 otherwise
? – – – res ? res res 0
SF=1 if result is 0 or positive
SF=0 if result is negative
ZF=1 if result equal to 0
ZF=0 if result not equal to 0
PF=1 if low byte of result has even number of set bits
PF=0 otherwise
CF=0 unless shift lengths are less than or
equal to the size of the shifted operand,
then:
CF=1 for carry or borrow to high-order bit
CF=0 otherwise
INTEGER DB -45 ; D3h
; signed division by 2: INTEGER = INTEGER / 2
SAR INTEGER,1 ; INTEGER = EAh = -22
; remainder in CF
POWER2 EQU 2 ; divide by 4
INTEGER DW -21 ; FFEBh
; signed division by 4: DX = DX / pow(2,POWER2)
MOV DX,INTEGER ; DX = FFEBh = -21
SAR DX,POWER2 ; DX = FFFBh = -5
; remainder is lost