LCD Panel Power Up/Down Timing
© 2009 Advanced Micro Devices, Inc.
45732 AMD 780E Databook 3.10
Proprietary
4-5
4.8
LCD Panel Power Up/Down Timing
Figure 4-2. LCD Panel Power Up/Down Timing
Table 4-6 LCD Power Up/Down Timing
Parameter
Description
Time (
s)
*
T1
Delay from LVDS_DIGON active to LVDS data/clock
M*N1
T2
Delay from LVDS data/clock to LVDS_BLON active
M*N2
T3
Delay from LVDS_BLON inactive to LVDS inactive
M*N2
T4
Delay from LVDS inactive to LVDS_DIGON inactive
M*N1
*Note:
Values for M, N1 and N2 are programmable through the following registers:
M = LVTMA_PWRSEQ_REF_DIV.LVTMA_PWRSEQ_REF_DIV (1- 255)
N1 = LVTMA_PWRSEQ_DELAY1.LVTMA_PWRUP_DELAY1 (0 - 15)
N2 = LVTMA_PWRSEQ_DELAY1.LVTMA_PWRUP_DELAY2 (0 - 15)
LVDS_DIGON
LVDS DATA/CLOCK
LVDS_BLON
T1
T2
T3
T4
LVDS_EN_BL
(CPIS)
PWM