DVI/HDMI™
© 2009 Advanced Micro Devices, Inc.
45732 AMD 780E Databook 3.10
Proprietary
2-13
2.5
DVI/HDMI™
2.5.1 DVI/HDMI™ Data Transmission Order and Signal Mapping
The RS780E contains two dual-link TMDS interfaces, multiplexed on the PCI Express
®
graphics lanes (see
section 3.9,
“TMDS Interface Multiplexed on the PCI Express® Graphics Lanes‚’ on page 3-10
) and on the LVTM interface (see
section 3.8, “LVTM Interface in TMDS Mode‚’ on page 3-9
), which support clock frequencies of up to 162 MHz on each
link.
Figure 2-8
shows the transmission ordering of the signals on the interfaces.
Figure 2-8 Data Transmission Ordering for the TMDS Interfaces
For dual-link mode, which is for DVI only, the same transmission order applies to data channels on the second link, with
the first link transmitting data for even pixels and the second link for odd pixels. See
Table 2-10
below for details.
The signal mapping for the transmission is shown in
Table 2-9
(single link) and
Table 2-10
(dual-link DVI) below.
TX0P
TX0M
TX1P
TX1M
TX2P
TX2M
TXCP
TXCM
TG9
TG8
TG7
TG6
TG5
TG4
TG3
TG2
TG1
TG0
Depending upon state of HSYNC and VSYNC
Depending upon encoded Green channel pixel data
Depending upon state of PLL_SYNC and CTL1
Depending upon state of CTL2 and CTL3
TR1
TR0
TR2
TR3
TR4
TR5
TR6
TR7
TR8
TR9
Depending upon encoded Red channel pixel data
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TB7
TB8
TB9
Depending upon encoded Blue channel pixel data
Various control and audio (for HDMI only) signals
Various control and audio (for HDMI only) signals
Various control and audio (for HDMI™ only) signals
Encoded Red Channel Pixel Data
Encoded Green Channel Pixel Data
Encoded Blue Channel Pixel Data