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AMD 780E Technical Reference Manual Download Page 54

45732 AMD 780E Databook 3.10

© 2009 Advanced Micro Devices, Inc.

3-14

Proprietary

Strapping Options

3.15

Strapping Options

The RS780E provides strapping options to define specific operating parameters. The strap values are latched into internal
registers after the assertion of the POWERGOOD signal to the RS780E.

Table 3-17, “Strap Definitions for the RS780E,”

shows the definitions of all the strap functions. These straps are set by one of the following four methods:

•

Attaching pull-up resistors to specific strap pins listed in

Table 3-17

to set their values to “1”.

•

Attaching pull-down resistors to specific strap pins listed in

Table 3-17

to set their values to “0”.

•

Downloading the strap values from an I

2

C™ serial EEPROM (for debug purpose only; contact your AMD CSS

representative for details).

•

Setting through an external debug port, if implemented (contact your AMD CSS representative for details).

All of the straps listed in

Table 3-17

are defined active low. To select “1”, the strap pins must be pulled up to VDD33

through resistors. To select “0”, the strap pins must be pulled down to VSS through resistors. During reset, the strap pins
are undriven, allowing the external pull-up or pull-down to pull a pin to “0” or “1.” The values on the strap pins are then
latched into the device and used as operational parameters. However, for debug purposes, those latched values may be
overridden through an external debug strap port or by a bit-stream downloaded from a serial EEPROM.

VSS

34

AA14, AB11, AB15, AB17,
AB19, AB21, AC12, AE14,
AE20, D11, E14, E15, G8, J12,
J15, K11, K14, L12, L15, M11,
M14, N13, P12, P15, R11,
R14, T12, U11, U14, U15, V12,
W11, W15, Y18

Common Ground

VSSAHT

27

A25, AD25, D23, E22, G22,
G24, G25, H19, H20, J22,
L17, L22, L24, L25, M20, N22,
P20, R19, R22, R24, R25,
U22, V19, W22, W24, W25,
Y21

Ground pin for HyperTransport interface PLL

VSSAPCIE

40

A2, AA4, AB1, AB2, AB5, AB7,
AC3, AC4, AE1, AE4, B1, D3,
D5, E4, G1, G2, G4, H7, J4,
L1, L2, L4, L7, M6, N4, P6, R1,
R2, R4, R7, U4, V6, V7, V8,
W1, W2, W4, W7, W8, Y6

Ground for PCI Express

®

Interface

VSSLT

7

C14, C16, C18, C20, C22,
D15, E20

Ground for LVDS interface

VSSLTP18

1

B13

Ground for LVDS interface PLL macro

Total Ground Pin Count

116

Table 3-16 Ground Pins (Continued)

Pin Name

Pin Count

Ball Reference

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Summary of Contents for 780E

Page 1: ...AMD 780E Databook Technical Reference Manual Rev 3 10 P N 45732_rs780e_ds_pub 2009 Advanced Micro Devices Inc ...

Page 2: ...w are trademarks of Advanced Micro Devices Inc DisplayPort is a trademark of VESA HDMI the HDMI Logo and High Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC HyperTransport is a licensed trademark of the HyperTransport Technology Consortium I2 C is a trademark of Philips Linux is a registered trademark of Linus Torvalds Macrovision is a registered trad...

Page 3: ...16 PC Design Guide Compliance 1 8 1 2 17 Test Capability Features 1 9 1 2 18 Additional Features 1 9 1 2 19 Packaging 1 9 1 3 Software Features 1 9 1 4 Branding Diagram 1 10 1 5 Graphics Device ID and Graphics Engine Clock Speed 1 10 1 6 Conventions and Notations 1 10 1 6 1 Pin Names 1 10 1 6 2 Pin Types 1 10 1 6 3 Numeric Representation 1 11 1 6 4 Register Field 1 11 1 6 5 Hyperlinks 1 11 1 6 6 A...

Page 4: ...ode 3 8 3 8 2 LVTM Interface in TMDS Mode 3 9 3 9 TMDS Interface Multiplexed on the PCI Express Graphics Lanes 3 10 3 10 DisplayPort Interface 3 10 3 11 Power Management Pins 3 11 3 12 Miscellaneous Pins 3 12 3 13 Power Pins 3 12 3 14 Ground Pins 3 13 3 15 Strapping Options 3 14 Chapter 4 Timing Specifications 4 1 HyperTransportTM Bus Timing 4 1 4 2 HyperTransportTM Reference Clock Timing Paramete...

Page 5: ...apabilities List Data Structure in PCI Configuration Space 6 2 6 2 4 Register Block Definition 6 3 6 2 5 Capability Identifier CAP_ID Offset 0 6 4 6 2 6 Next Item Pointer Offset 1 6 5 6 2 7 PMC Power Management Capabilities Offset 2 6 6 Chapter 7 Testability 7 1 Test Capability Features 7 1 7 2 Test Interface 7 1 7 3 XOR Test 7 1 7 3 1 Description of a Generic XOR Tree 7 1 7 3 2 Description of the...

Page 6: ...AMD 780E Databook 3 10 2009 Advanced Micro Devices Inc Table of Contents 4 Proprietary Table of Contents This page is left blank intentionally ...

Page 7: ... Transmission Ordering for the TMDS Interfaces 2 13 Figure 2 9 Pins for Analog Output on the DVI I Connector 2 18 Figure 3 1 RS780E Pin Assignment Top View Left 3 2 Figure 3 2 RS780E Pin Assignment Top View Right 3 3 Figure 3 3 RS780E Interface Block Diagram 3 4 Figure 4 1 RS780E Power Rail Power up Sequence 4 4 Figure 4 2 LCD Panel Power Up Down Timing 4 5 Figure 5 1 DC Characteristics of the TMD...

Page 8: ...AMD 780E Databook 3 10 2009 Advanced Micro Devices Inc List of Figures 2 Proprietary List of Figures This page is left blank intentionally ...

Page 9: ... 8 Table 3 10 LVTM Interface in TMDS Mode 3 9 Table 3 11 TMDS Interface Multiplexed on the PCI Express Graphics Interface 3 10 Table 3 12 DisplayPort Interface Multiplexed on the PCI Express Graphics Interface 3 11 Table 3 13 Power Management Pins 3 11 Table 3 14 Miscellaneous Pins 3 12 Table 3 15 Power Pins 3 12 Table 3 16 Ground Pins 3 13 Table 3 17 Strap Definitions for the RS780E 3 15 Table 4 ...

Page 10: ...2 ACPI Signal Definitions 6 1 Table 6 3 Standard PCI Configuration Space Header Type 0 6 2 Table 6 4 PCI Status Register 6 3 Table 6 5 Capabilities Pointer CAP_PTR 6 3 Table 6 6 Power Management Register Block 6 3 Table 6 7 Power Management Control Status Register PMCSR 6 4 Table 6 8 Capability Identifier CAP_ID 6 4 Table 6 9 Next Item Pointer NEXT_ITEM_PTR 6 5 Table 6 10 Power Management Capabili...

Page 11: ...rate the Windows Vista desktop even under the most demanding circumstances The ATI M72 based graphics core employs a unified shader architecture to deliver optimal 3D performance across the whole spectrum of 3D applications This future proof core ensures compatibility with both current and upcoming 3D applications and meets Windows Vista Premium Logo requirements through 2008 and beyond Leading Mu...

Page 12: ...tter mode 1 2 2 Memory Interface Supports an optional dedicated local frame buffer side port of up to 128MB through a 16 bit interface Note however that the memory interface is optimized for a 64MB local frame buffer New highly flexible memory architecture allows asymmetric side port and shared system memory frame buffer sizes Supported configurations include UMA only and UMA side port interleave ...

Page 13: ...layout when the end device does not support lane reversal Supports six general purpose lanes for up to six devices on specific ports Possible configurations are listed in Table 1 1 Table 1 1 Possible Configurations for the PCI E General Purpose Links Config B Config C Config C2 Config E Config K Config L GPP1 x4 x4 x2 x2 x2 x1 GPP2 x1 GPP3 x2 x1 x2 x1 GPP4 x1 x1 GPP5 x2 x1 x2 x1 x1 x1 GPP6 x1 x1 x...

Page 14: ...for GDI extensions In Windows XP and Windows Vista Alpha BLT Transparent BLT and Gradient Fill In Windows 7 Alpha BLT Transparent BLT Color Fill BLT Stretch BLT and Clear Type BLT Hardware cursor up to 64x64x32bpp with alpha channel for direct support of Windows XP Windows Vista and Windows 7 alpha cursor 1 2 7 3D Acceleration Features Fully DirectX 10 0 compliant including full speed 32 bit float...

Page 15: ...us designs High efficiency ring bus memory controller Programmable arbitration logic maximizes memory efficiency software upgradeable Fully associative texture color and Z cache design New hierarchical Z and stencil buffers with early Z Test New lossless Z buffer compression for both Z and stencil Fast Z Buffer Clear Z cache optimized for real time shadow rendering Z and color compression resource...

Page 16: ...pports 8 16 32 and 64 bpp depths for the main graphics layer For 32 bpp depth supports xRGB 8 8 8 8 xRGB 2 10 10 10 sCrYCb 8 8 8 8 and xCrYCb 2 10 10 10 data formats For 64 bpp depth supports xRGB 16 16 16 16 data format Independent gamma color conversion and correction controls for main graphics layer Support for DDC1 and DDC2B for plug and play monitors 8 bit alpha blending of graphics and video...

Page 17: ...cluding 480p 720p 1080i and 1080p for a full list of currently supported modes contact you AMD CSS representative Maximum resolutions supported by various modes are Single link DVI 1600x1200 60Hz with standard timings and 1920x1200 60Hz with reduced blanking timings Dual link DVI 2560x1600 60Hz HDMI 1080p Supports YCbCr 4 4 4 and 4 2 2 modes with HDMI HDMI basic audio support at 32 44 1 or 48 kHz ...

Page 18: ... 1 1V CMOS technology Supports ACPI 2 0 for S0 S3 S4 and S5 states Full IAPC Instantly Available PC power management support Static and dynamic power management support APM as well as ACPI with full VESA DPM and Energy Star compliance The Chip Power Management Support logic supports four device power states defined for the OnNow Architecture On Standby Suspend and Off Each power state can be achie...

Page 19: ...nstruction register of the JTAG circuitry 1 2 18 Additional Features Integrated spread spectrum PLLs on the memory and LVDS interface 1 2 19 Packaging Single chip solution in 55nm 1 1V low power CMOS technology 528 FCBGA package 21mmx21mm 1 3 Software Features BIOS ability to read EDID 1 1 1 2 and 1 3 Ability to selectively enable and disable several devices including CRT LCD and DFP Register comp...

Page 20: ...times assume alternate functional names when they perform their alternate functions and these functional names are given in Chapter 3 Pin Descriptions and Strap Options All active low signals are identified by the suffix in their names e g MEM_RAS 1 6 2 Pin Types The pins are assigned different codes according to their operational characteristics These codes are listed in Table 1 3 Variant Graphic...

Page 21: ...e PDF version of this manual can click on the links to go directly to the referenced sections tables or figures 1 6 6 Acronyms and Abbreviations The following is a list of the acronyms and abbreviations used in this manual Pwr Power Gnd Ground A O Analog Output A I Analog Input A I O Analog Bi Directional Input Output A Pwr Analog Power A Gnd Analog Ground Other Pin types not included in any of th...

Page 22: ... An IEEE standard LVDS Low Voltage Differential Signaling MB Mega Byte MPEG Motion Pictures Experts Group Refers to compressed video image streams in either MPEG 1 or MPEG 2 formats NTSC National Television Standards Committee The standard definition TV system used in North America and other areas PAL Phase Alternate Line The standard definition TV system used in Europe and other areas PCI Periphe...

Page 23: ...This section presents an overview of the HyperTransport interface For a detailed description of the interface please refer to the HyperTransport Unit CPU Interface Register Interface UVD Setup Engine 2D Engine 3D Engine Overlay Root MUX Display 1 2 CRT Memory Controller AMD CPU Bus Interface Complex Optional 16 bit DDR2 DDR3 Memory Channel TMDS enabling DVI HDMI SB External Graphics A Link E II Gf...

Page 24: ...lization and configuration sequences periodic redundancy checks connect disconnect sequences and information packet flow controls The protocol layer is responsible for maintaining strict ordering rules defined by the HT protocol The RS780E HyperTransport bus interface consists of eighteen unidirectional differential data control pairs and two differential clock pairs in each of the upstream and do...

Page 25: ...e that significantly increases the memory bandwidth and reduces data latency to the integrated graphics core The additional bandwidth provided to the internal graphics core will also aid the RS780E in reaching and exceeding Microsoft s Windows Vista Premium logo requirements 2 2 1 DDR2 Memory Interface Figure 2 4 RS780E Side Port Memory Interface on page 2 4 illustrates the side port memory interf...

Page 26: ...DDR2 Memory Row and Column Addressing Table 2 1 Supported DDR2 Components DDR2 SDRAM Mbytes Config Mbits CS Mode Bank Bits Row Bits Col Bits 16Mbx16 256 4 2 13 9 32 32Mbx16 512 10 2 13 10 64 64Mbx16 1024 11 3 13 10 128 Address A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 16Mbx16 devices Row P10 P14 P13 P12 P11 P22 P21 P20 P19 P18 P17 P16 P15 Column PC P9 P8 P7 P6 P5 P4 P3 P2 P1 32Mbx16 devices Ro...

Page 27: ... Table 2 4 shows how the physical address P after taking out the bank bit is used to provide the row and column addressing for each size of DDR3 memories Table 2 4 DDR3 Memory Row and Column Addressing 64Mbx16 devices Row P23 P14 P13 P12 P11 P22 P21 P20 P19 P18 P17 P16 P15 Column PC P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 128Mbx16 devices Row P24 P23 P14 P13 P12 P11 P22 P21 P20 P19 P18 P17 P16 P15 Column P...

Page 28: ...0E Notice that the RS780E can also provide a TMDS output via its TMDS interface that is multiplexed with its PCI Express graphics link As a result the RS780E can provide two digital display outputs using its two on chip integrated TMDS transmitters one through the LVTM interface and the other through the TMDS interface multiplexed with the PCI E graphics interface TXOUT_U0N P TXOUT_U1N P TXOUT_U2N...

Page 29: ...on are shown in Table 2 5 and Table 2 6 respectively Figure 2 7 shows the transmission ordering of the LVDS signals for 24 bit transmission on the lower and the upper data channels The signal mappings for single and dual channel transmission are shown in Table 2 9 and Table 2 10 respectively Figure 2 6 Single Dual Channel 18 bit LVDS Data Transmission Ordering LP1C1 LP1C2 LP1C3 T Cycle LP1C4 LP1C5...

Page 30: ... 2 5 LVDS 18 bit TFT Single Pixel per Clock Single Channel Signal Mapping TX Signal 18 bit LP1C1 R0 LP1C2 R1 LP1C3 R2 LP1C4 R3 LP1C5 R4 LP1C6 R5 LP1C7 G0 LP2C1 G1 LP2C2 G2 LP2C3 G3 LP2C4 G4 LP2C5 G5 LP2C6 B0 LP2C7 B1 LP3C1 B2 LP3C2 B3 LP3C3 B4 LP3C4 B5 LP3C5 HSYNC LP3C6 VSYNC LP3C7 ENABLE ...

Page 31: ...3 UP1C4 Re3 LP1C5 Ro4 UP1C5 Re4 LP1C6 Ro5 UP1C6 Re5 LP1C7 Go0 UP1C7 Ge0 LP2C1 Go1 UP2C1 Ge1 LP2C2 Go2 UP2C2 Ge2 LP2C3 Go3 UP2C3 Ge3 LP2C4 Go4 UP2C4 Ge4 LP2C5 Go5 UP2C5 Ge5 LP2C6 Bo0 UP2C6 Be0 LP2C7 Bo1 UP2C7 Be1 LP3C1 Bo2 UP3C1 Be2 LP3C2 Bo3 UP3C2 Be3 LP3C3 Bo4 UP3C3 Be4 LP3C4 Bo5 UP3C4 Be5 LP3C5 HSYNC UP3C5 from the register LP3C6 VSYNC UP3C6 from the register LP3C7 ENABLE UP3C7 from the register...

Page 32: ...gure 2 7 Single Dual Channel 24 bit LVDS Data Transmission Ordering UP1C1 UP1C2 UP1C3 T Cycle UP1C4 UP1C5 UP1C6 UP1C7 TXOUT_U0 UP2C1 UP2C2 UP2C3 UP2C4 UP2C5 UP2C6 UP2C7 TXOUT_U1 UP3C1 UP3C2 UP3C3 UP3C4 UP3C5 UP3C6 UP3C7 TXOUT_U2 TXCLK_U UP4C1 UP4C2 UP4C3 UP4C4 UP4C5 UP4C6 UP4C7 TXOUT_U3 ...

Page 33: ...per Clock Single Channel Signal Mapping TX Signal 24 bit LP1C1 R0 LP1C2 R1 LP1C3 R2 LP1C4 R3 LP1C5 R4 LP1C6 R5 LP1C7 G0 LP2C1 G1 LP2C2 G2 LP2C3 G3 LP2C4 G4 LP2C5 G5 LP2C6 B0 LP2C7 B1 LP3C1 B2 LP3C2 B3 LP3C3 B4 LP3C4 B5 LP3C5 HSYNC LP3C6 VSYNC LP3C7 ENABLE LP4C1 R6 LP4C2 R7 LP4C3 G6 LP4C4 G7 LP4C5 B6 LP4C6 B7 LP4C7 Reserved ...

Page 34: ... and the modulation frequency in the range of 20 50kHz are programmable through the LVDS registers TX Signal 24 bit TX Signal 24 bit LP1C1 Ro0 UP1C1 Re0 LP1C2 Ro1 UP1C2 Re1 LP1C3 Ro2 UP1C3 Re2 LP1C4 Ro3 UP1C4 Re3 LP1C5 Ro4 UP1C5 Re4 LP1C6 Ro5 UP1C6 Re5 LP1C7 Go0 UP1C7 Ge0 LP2C1 Go1 UP2C1 Ge1 LP2C2 Go2 UP2C2 Ge2 LP2C3 Go3 UP2C3 Ge3 LP2C4 Go4 UP2C4 Ge4 LP2C5 Go5 UP2C5 Ge5 LP2C6 Bo0 UP2C6 Be0 LP2C7 B...

Page 35: ...nnels on the second link with the first link transmitting data for even pixels and the second link for odd pixels See Table 2 10 below for details The signal mapping for the transmission is shown in Table 2 9 single link and Table 2 10 dual link DVI below TX0P TX0M TX1P TX1M TX2P TX2M TXCP TXCM TG9 TG8 TG7 TG6 TG5 TG4 TG3 TG2 TG1 TG0 Depending upon state of HSYNC and VSYNC Depending upon encoded G...

Page 36: ...Phase 2 B1 Phase 3 B2 Phase 4 B3 Phase 5 B4 Phase 6 B5 Phase 7 B6 Phase 8 B7 Phase 9 B8 Phase 10 B9 TX1M P Phase 1 G0 Phase 2 G1 Phase 3 G2 Phase 4 G3 Phase 5 G4 Phase 6 G5 Phase 7 G6 Phase 8 G7 Phase 9 G8 Phase 10 G9 TX2M P Phase 1 R0 Phase 2 R1 Phase 3 R2 Phase 4 R3 Phase 5 R4 Phase 6 R5 Phase 7 R6 Phase 8 R7 Phase 9 R8 Phase 10 R9 Note H VSYNC are transmitted on TX0M P Blue channel during blank...

Page 37: ...hase 2 EVEN_G1 Phase 2 ODD_G1 Phase 3 EVEN_G2 Phase 3 ODD_G2 Phase 4 EVEN_G3 Phase 4 ODD_G3 Phase 5 EVEN_G4 Phase 5 ODD_G4 Phase 6 EVEN_G5 Phase 6 ODD_G5 Phase 7 EVEN_G6 Phase 7 ODD_G6 Phase 8 EVEN_G7 Phase 8 ODD_G7 Phase 9 EVEN_G8 Phase 9 ODD_G8 Phase 10 EVEN_G9 Phase 10 ODD_G9 TX2M P Phase 1 EVEN_R0 TX5M P Phase 1 ODD_R0 Phase 2 EVEN_R1 Phase 2 ODD_R1 Phase 3 EVEN_R2 Phase 3 ODD_R2 Phase 4 EVEN_...

Page 38: ...0x03 General Control No Sending and contents controlled by video driver 0x04 ACP Packet No 0x05 ISRC1 Packet No 0x06 ISRC2 Packet No 0x07 Reserved N A N A N A InfoFrame Packet Type HDMI ID EIA 861B ID 0x80 0x00 Vendor Specific Yes 0x81 0x01 AVI Yes Inserted on line selected by software For colorimetry repetition count video format picture formatting 0x82 0x02 Source Product Descriptor Yes 0x83 0x0...

Page 39: ...ion 5 Linearity measured from the best fit line through the DAC characteristics Monotonicity guaranteed 6 Load 37 5 20 pF with Iref 1 50 mA Iref is the current flowing out of the Rset resistor 7 Measured from the end of the overshoot to the point where the amplitude of the video ringing is down to 5 of the final steady state value 8 This parameter is sampled not 100 tested 9 Monotonicity is guaran...

Page 40: ...ctor For the DVI output portion of the DVI I connector AMD recommends using the RS780E s LVTM interface to provide the DVI output and routing these digital signals see section 2 3 LVTM LVDS TMDS Interface on page 2 6 to the appropriate inputs on the DVI I connector The video BIOS must be configured so that the RS780E drives out DVI signals from its LVTM interface Display modes supported include de...

Page 41: ...ace on page 3 5 PCI Express Interfaces on page 3 6 1 x 16 or 2 x 8 Lane Interface for External Graphics on page 3 6 A Link Express II Interface for Southbridge on page 3 6 6 x 1 Lane Interface for General Purpose External Devices on page 3 6 Miscellaneous PCI Express Signals on page 3 6 Clock Interface on page 3 7 CRT Interface on page 3 7 LVTM Interface on page 3 8 TMDS Interface Multiplexed on t...

Page 42: ...CIE GFX_RX9N VDDPCIE VDDA18PCIE VDDC VSS M GFX_TX13P GFX_TX13N GFX_TX12N GFX_TX12P GFX_RX11N VSSAPCIE GFX_RX10N GFX_RX9P VDDPCIE VDDA18PCIE VSS VDDC VDDC N GFX_TX14N GFX_TX14P VSSAPCIE VDDC VSS P GFX_TX15P GFX_TX15N GFX_RX14N GFX_RX14P GFX_RX11P VSSAPCIE GFX_RX10P GFX_RX12N VDDPCIE VDDA18PCIE VDDC VSS VDDC R VSSAPCIE VSSAPCIE VSSAPCIE GFX_RX13N GFX_RX13P VSSAPCIE GFX_RX12P VDDPCIE VDDA18PCIE VSS V...

Page 43: ...TXCAD14P HT_RXCTL0P HT_RXCTL0N HT_TXCTL0P HT_TXCTL0N M VDDC VSSAHT HT_RXCAD7P HT_RXCAD7N N VDDC VSS VDDHT VDDHTTX HT_TXCAD15P HT_TXCTL1P VSSAHT HT_TXCAD14N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6N HT_RXCAD6P P VSS VDDC VDDHT VDDHTTX HT_TXCTL1N VSSAHT HT_RXCTL1N HT_RXCTL1P VSSAHT VSSAHT VSSAHT R VDDC VDDC VDDHT VDDHTTX HT_RXCLK0P HT_RXCLK0N HT_RXCAD4N HT_RXCAD4P T VSS VSS VDDC VDDHTTX HT_RXCAD15 HT_RXCAD15...

Page 44: ...T RED RED GREEN GREEN DAC_SCL DAC_SDA DAC_HSYNC DAC_VSYNC BLUE BLUE THERMALDIODE_P HT Interface LVTM Interface A Link Express II Interface Power Management Interface Misc Signals PCI E External Graphics or TMDS Interface CRT Interface Clock Interface Power Grounds VDDHTRX AVSSDI LVDS_DIGON LVDS_BLON PCI E Interface for General Purpose External Devices GPP_TX 5 0 P GPP_TX 5 0 N GPP_RX 5 0 P GPP_RX ...

Page 45: ...Transmitter Calibration Resistor to HTTX_CALN HT_TXCALN Other VDDHTTX VSS Transmitter Calibration Resistor to HTTX_CALP Table 3 2 Side Port Memory Interface Pin Name Type Power Domain Ground Domain Integrated Termination Functional Description MEM_A 13 0 O VDD_MEM VSS None Memory Address Bus Provides the multiplexed row and column addresses to the memory MEM_BA 2 0 O VDD_MEM VSS None Memory Bank A...

Page 46: ...N I VDDPCIE VSSAPCIE 50 between complements Receive Data Differential Pairs Connect to external connector for an external graphics card on the motherboard if implemented Table 3 4 1 x 4 Lane A Link Express II Interface for Southbridge Pin Name Type Power Domain Ground Domain Integrated Termination Functional Description SB_TX 3 0 P SB_TX 3 0 N O VDDPCIE VSSAPCIE 50 between complements Transmit Dat...

Page 47: ...general purpose PCI E devices Not used Can be left unconnected or connected to the external clock generator for maintaining system compatibility with the RX780 or RD780 REFCLK_P REFCLK_N I VDD33 VSS Reference clock input for the RS780E REFCLK_P is a single ended 14 31818MHz input from the external clock generator input swing should be 1 1V Connect REFCLK_N to VREF 0 55V on the motherboard Table 3 ...

Page 48: ...VSSR None LVDS upper clock channel Only used in dual channel LVDS mode TXOUT_L0N O VDDLT18 LVSSR None LVDS lower data channel 0 This channel is used as the transmitting channel in single channel LVDS mode TXOUT_L0P O VDDLT18 LVSSR None LVDS lower data channel 0 This channel is used as the transmitting channel in single channel LVDS mode TXOUT_L1N O VDDLT18 LVSSR None LVDS lower data channel 1 This...

Page 49: ...S_DIGON I O VDD33 VSS 50k programmable PU PD none Control Panel Digital Power On Off Active high LVDS_EN_BL I O VDD33 VSS 50k programmable PU PD none Enables Backlight for CPIS compliant LCD panels Active high Controlled by the hardware power up down sequencer For more details refer to Figure 4 2 LCD Panel Power Up Down Timing on page 4 5 Table 3 10 LVTM Interface in TMDS Mode Pin Name TMDS Functi...

Page 50: ...el is only used in DVI dual link mode and is not used for HDMI support TXOUT_U1P TX5P O VDDLT18 VSSLT None TMDS data channel 5 The channel is only used in DVI dual link mode and is not used for HDMI support TXOUT_U2N O VDDLT18 VSSLT None Unused NC TXOUT_U2P O VDDLT18 VSSLT None Unused NC TXOUT_U3N O VDDLT18 VSSLT None Unused NC TXOUT_U3P O VDDLT18 VSSLT None Unused NC TXCLK_LN TXCM O VDDLT18 VSSLT...

Page 51: ...air 3 on the second DisplayPort connector DDC_CLK1 AUX1P DDC_DATA1 AUX1N B7 A7 Auxiliary Channel Pair 1 on the second DisplayPort connector AUX_CAL C8 Calibration for auxiliary pads Table 3 13 Power Management Pins Pin Name Type Power Domain Ground Domain Functional Description ALLOW_LDTSTOP I OD VDD33 VSS Allow LDTSTOP The signal is used for controlling LDTSTOP assertions When running in CLMC mod...

Page 52: ...k signal It can also be used as GPIO The signal is 5V tolerant I2C_DATA I O VDD33 VSS 50k programmable PU PD none I2C interface data signal It can also be used as GPIO The signal is 5V tolerant NC No connect These pins should be left unconnected to anything STRP_DATA I O VDD33 VSS 50k programmable PU PD none I2 C interface data signal for external EEPROM based strap loading Can also be used as GPI...

Page 53: ...2 F9 G9 1 8V I O transform power VDD33 3 3V 2 H11 H12 3 3V I O power VDDHT 1 1V 7 J17 K16 L16 M16 P16 R16 T16 Digital I O power for HyperTransport interface VDDHTRX 1 1V 7 A23 B23 D22 E21 F20 G19 H18 I O power for HyperTransport receive interface VDDHTTX 1 2V 13 AA21 AB22 AC23 AD24 AE25 M17 P17 R17 T17 U17 V18 W19 Y20 I O power for HyperTransport transmit interface VDDLT18 1 8V 2 A15 B15 1 8V I O ...

Page 54: ...ulled up to VDD33 through resistors To select 0 the strap pins must be pulled down to VSS through resistors During reset the strap pins are undriven allowing the external pull up or pull down to pull a pin to 0 or 1 The values on the strap pins are then latched into the device and used as operational parameters However for debug purposes those latched values may be overridden through an external d...

Page 55: ...ues from EEPROM 0 I2C master can load strap values from EEPROM if connected or use default values if EEPROM is not connected Please refer to RS780E s reference schematics for system level implementation details 1 Use default values Note On the RS780E the widths of the A Link Express II interface and the general purpose PCI E links are configured through the programmable strap GPPSB_LINK_CONFIG whi...

Page 56: ...45732 AMD 780E Databook 3 10 2009 Advanced Micro Devices Inc 3 16 Proprietary Strapping Options This page intentionally left blank ...

Page 57: ...tion and AMD Family 10h Processor Reference Clock Parameters order 34864 1 Single ended measurement at crossing point Value is maximum minimum over all time DC value of common mode is not important due to blocking cap 2 Minimum frequency is a consequence of 0 5 down spread spectrum 3 Measured with spread spectrum turned off 4 Only simulated at the receive die pad This parameter is intended to give...

Page 58: ...eriod is 5ns then DQS1 is delayed internally by 1 25ns with respect to DQ 15 8 Table 4 2 PCI E Differential Clock GFX_REFCLK GPPSB_REFCLK 100MHz AC Characteristics Symbol Description Minimum Maximum Unit Rising Edge Rate Rising Edge Rate 0 6 4 0 V ns Falling Edge Rate Falling Edge Rate 0 6 4 0 V ns TPERIOD AVG Average Clock Period Aquaria 300 2800 ppm TPERIOD ABS Absolute Period including jitter a...

Page 59: ...ly by 2 5ns with respect to DQ 7 0 Depending on the board layout of DQS and DQ signals it may be necessary to have different delays for each DQS signal Layouts of the DQS and DQ signals should follow the rules given in the AMD RS740 RS780 Series IGP Motherboard Design Guide order 42336 4 6 LVDS Timing Table 4 4 Timing Requirements for the LVTM Interface in LVDS Mode Parameter Min Typ Max Unit Note...

Page 60: ...elative to 1 8V Display PLL and I O Transform rails 0 2 1 T12 1 8V Display PLL and I O Transform rails ramp high relative to 1 1V PLL rails 0 No restrictions T13 1 1V PLL rails ramp high relative to VDDC 1 1V 0 No restrictions T11 T12 T13 3 3V Rails AVDD VDD33 1 8V Display PLL and IO Transform Rails PLLVDD18 IOPLLVDD18 VDDLT18 VDDLTP18 VDDA18HTPLL VDDA18PCIEPLL AVDDDI AVDDQ VDD18 1 1V PLL Rails PL...

Page 61: ...e to LVDS data clock M N1 T2 Delay from LVDS data clock to LVDS_BLON active M N2 T3 Delay from LVDS_BLON inactive to LVDS inactive M N2 T4 Delay from LVDS inactive to LVDS_DIGON inactive M N1 Note Values for M N1 and N2 are programmable through the following registers M LVTMA_PWRSEQ_REF_DIV LVTMA_PWRSEQ_REF_DIV 1 255 N1 LVTMA_PWRSEQ_DELAY1 LVTMA_PWRUP_DELAY1 0 15 N2 LVTMA_PWRSEQ_DELAY1 LVTMA_PWRUP...

Page 62: ...45732 AMD 780E Databook 3 10 2009 Advanced Micro Devices Inc 4 6 Proprietary LCD Panel Power Up Down Timing This page is left blank intentionally ...

Page 63: ...ide port memory interface VDDA18HTPLL 1 71 1 8 1 89 V I O power for HyperTransport PLL VDDA18PCIE 1 71 1 8 1 89 V 1 8V I O power for PCI E graphics SB and GPP interfaces VDDA18PCIEPLL 1 71 1 8 1 89 V 1 8V I O power for PCI E PLLs VDDC 0 95 1 0 1 1 1 155 V Core power Note Variable core voltage is not supported on platforms that support either a PCI E Gen2 or b DDR3 1200 side port frame buffer memor...

Page 64: ...N DDC_CLK0 AUX0P DDC_DATA1 AUX1N DDC_CLK1 AUX1P VILdc DC voltage at PAD pin that will produce a stable low at the Y pin of macro TBD V 1 VIHdc DC voltage at PAD pin that will produce a stable high at the Y pin of macro 1 8 V 1 VILac AC input low voltage TBD V VIHac AC input high voltage 2 3 V VOL Output low voltage 86mV I 3mA 230mV I 8mA V 2 3 4 VOH Output high voltage VDD5 0 25 VDD5 is external 5...

Page 65: ...tion Minimum Maximum Unit Note VIL Single Input Low Voltage 0 40 V 1 VIH Single Input High Voltage 0 70 V 2 VIMAX Absolute Max Input Voltage 1 15 V VIMIN Absolute Min Input Voltage 0 15 V ZC DC Clock source DC impedance 40 60 Notes 1 VILmax VREF 0 15V where VREF 0 55V 2 VIHmin VREF 0 15V where VREF 0 55V Symbol Description Minimum Maximum Comments VIL dc DC Input Low Voltage 0 3V VREF 0 15V For DQ...

Page 66: ...Current 16 5mA 24 3mA IOH Output High Current 15 8mA 24 6mA CIN Input Capacitance 3pF 5pF Table 5 10 DC Characteristics for the LVTM Interface in TMDS Mode Symbol Parameter Min Typical Max Unit Note VH Single ended High Level Output Voltage AVCC 10 AVCC 10 mV 1 VL Single ended Low Level Output Voltage AVCC 600 AVCC 400 mV 1 VSW Single ended Output Swing 400 600 mV VOS Differential Output Overshoot...

Page 67: ...evel Output Voltage AVCC 10 AVCC 10 mV 1 VL Single ended Low Level Output Voltage AVCC 600 AVCC 400 mV 1 VSW Single ended Output Swing 400 600 mV VOS Differential Output Overshoot Ringing 15 2VSW VUS Differential Output Undershoot Ringing 25 2VSW Notes 1 AVCC stands for the termination supply voltage of the receiver which is 3 3V 5 2 Figure 5 1 below illustrates some of the DC Characteristics of t...

Page 68: ...OS Differential Output Overshoot Ringing 160 mV 1 VUS Differential Output Undershoot Ringing 160 mV 1 IDDLP Average Supply Current at LTPVDD18 10 0 mA 2 IDDLV Average Supply Current at VDDLT18 33 100 0 mA 2 IOL Output Low Current 2 5 mA IOH Output High Current 4 5 mA IPDLP Power Down Current at LTPVDD18 10 0 A 3 IPDLV Power Down Current at VDDLT18 33 10 0 A 3 Notes 1 Differential termination is 10...

Page 69: ...ia a thermocouple based on the methodology given in the document Thermal Design and Analysis Guidelines for the RS780 Product Family order 44638 Chapter 12 This is the temperature at which the functionality of the chip is qualified 2 The maximum absolute rated junction temperature is the junction temperature at which the device can operate without causing damage to the ASIC This temperature can be...

Page 70: ...voltage readings one using current I and the other using current N x I N Ratio of the two thermal diode currents 10 when using an ADI thermal sensor e g ADM 1020 1030 Ideality factor of the diode K Boltzman s Constant T Temperature in Kelvin q Electron charge The series resistance of the thermal diode RT must be taken into account as it introduces an error in the reading for every 1 0 approximatel...

Page 71: ... ball arrangement for the RS780E Figure 5 1 RS780E 528 Pin FCBGA Package Outline Table 5 15 RS780E 528 Pin FCBGA Package Physical Dimensions Ref Min mm Typical mm Max mm c 0 48 0 58 0 68 A 1 69 1 84 1 99 A1 0 30 0 40 0 50 A2 0 81 0 86 0 91 b 0 40 0 50 0 60 D1 20 85 21 00 21 15 D2 8 58 D3 2 00 D4 1 00 E1 20 85 21 00 21 15 E2 7 70 E3 2 00 E4 1 00 F1 19 20 F2 19 20 e1 0 80 min pitch ddd 0 20 Note Max...

Page 72: ... and the die does not exceed 6 lbf Note that a total load of 4 6 lbf is adequate to secure the thermal management device and achieve the lowest thermal contact resistance with a temperature drop across the thermal interface material of no more than 3 C Also the surface flatness of the metal spreader should be 0 001 inch 1 inch Pre test the assembly fixture with a strain gauge to make sure that the...

Page 73: ...e Pads on PCB 5 3 3 2 Reflow Profile A reference reflow profile is given below Please note the following when using RoHS lead free solder SAC105 305 405 Tin Silver Cu The final reflow temperature profile will depend on the type of solder paste and chemistry of flux used in the SMT process Modifications to the reference reflow profile may be required in order to accommodate the requirements of the ...

Page 74: ...5 405 Tin Silver Copper Reflow Profile Table 5 16 Recommended Board Solder Reflow Profile RoHS Lead Free Solder Profiling Stage Temperature Process Range Overall Preheat Room temp to 220 C 2 mins to 4 mins Soaking Time 130 C to 170 C Typical 60 80 seconds Liquidus 220 C Typical 60 80 seconds Ramp Rate Ramp up and Cooling 2 C second Peak Max 245 C 235 C 5 C Temperature at peak within 5 C 240 C to 2...

Page 75: ... RS780E power off Processor States S0 C0 Working State Working State The processor is executing instructions S0 C1 Halt CPU Halt state No instructions are executed This state has the lowest latency on resume and contributes minimum power savings S0 C2 Stop Grant Caches Snoopable Stop Grant or Cache Snoopable CPU state This state offers more power savings but has a higher latency on resume than the...

Page 76: ...ng Power Status Reporting Setting Power State System Wakeup All four of these capabilities are required for each power management function with the exception of wakeup event generation This section describes the format of the registers in the PCI Configuration Space that are used by these power management operations The Status and Capabilities Pointer CAP_PTR fields have been highlighted to indica...

Page 77: ...as bytes 16 bit words or 32 bit DWORDs All of the write operations to the reserved registers must be treated as no ops This implies that the access must be completed normally on the bus and the data should be discarded Read accesses to the reserved or the unimplemented registers must be completed normally and a data value of 0000h should be returned Table 6 4 PCI Status Register Bits Default Value...

Page 78: ...olute offset in the functions PCI Configuration Space to the next item in the list and must be DWORD aligned If there are no more entries in the list the NEXT_ITEM_PTR must be set to 0 to indicate an end of the linked list Each capability can then have registers following the NEXT_ITEM_PTR The definition of these registers including layout size and bit definitions is specific to each capability Th...

Page 79: ...I Specifications for inclusion in the capabilities list or if power management is the last item in the list Table 6 9 Next Item Pointer NEXT_ITEM_PTR Bits Default Value Read Write Description 07 00 80h Read Only This field provides an offset in the PCI Configuration Space of the function pointing to the location of next item in the capability list of the function For Power Management of the RS780E...

Page 80: ...ignal while in that power state bit 11 XXXX1b PME can be asserted from D0 bit 12 XXX1Xb PME can be asserted from D1 bit 13 XX1XXb PME can be asserted from D2 bit 14 X0XXXb PME cannot be asserted from D3hot bit 15 0XXXXb PME cannot be asserted from D3cold 10 001b Read Only RS780E supports D2 09 001b Read Only RS780E supports D1 08 06 000b Read Only Reserved 05 1b Read Only The Device Specific Initi...

Page 81: ... characterization of these modules A JTAG test mode which is not entirely compliant to the IEEE 1149 1 standard to allow board level testing of neighboring devices An XOR TREE test mode on all the digital I O s to allow for proper soldering verification at the board level A VOH VOL test mode on all digital I O s to allow for proper verification of output high and output low voltages at the board l...

Page 82: ...ecommended for the XOR TREE test mode A pair of differential clock at 10MHz should also be supplied to HT_REFCLKP N to enable I Os for testing 7 3 4 XOR Tree for the RS780E The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the TDO Pin Refer to Table 7 3 for the list of the signals included on the XOR tree A toggle of any of these bal...

Page 83: ... 23 MEM_RAS W12 24 MEM_CAS Y12 25 MEM_BA0 AD16 26 MEM_BA1 AE17 27 MEM_BA2 AD17 28 MEM_A0 AB12 29 MEM_A1 AE16 30 MEM_A2 V11 31 MEM_A3 AE15 32 MEM_A4 AA12 33 MEM_A5 AB16 34 MEM_A6 AB14 35 MEM_A7 AD14 36 MEM_A8 AD13 37 MEM_A9 AD15 38 MEM_A10 AC16 39 MEM_A11 AE13 40 MEM_A12 AC14 41 MEM_A13 Y14 42 MEM_DQ0 AA18 43 MEM_DQ1 AA20 44 MEM_DQ2 AA19 45 MEM_DQ3 Y19 46 MEM_DQ4 V17 47 MEM_DQ5 AA17 48 MEM_DQ6 AA15...

Page 84: ... GFX_RX9P N M8 L8 73 GFX_RX10P N P7 M7 74 GFX_RX11P N P5 M5 75 GFX_RX12P N R8 P8 76 GFX_RX13P N R6 R5 77 GFX_RX14P N P4 P3 78 GFX_RX15P N T4 T3 79 GPP_RX0P N AE3 AD4 80 GPP_RX1P N AE2 AD3 81 GPP_RX2P N AD1 AD2 82 GPP_RX3P N V5 W6 83 GPP_RX4P N U5 U6 84 GPP_RX5P N U8 U7 85 SB_RX0P N AA8 Y8 86 SB_RX1P N AA7 Y7 87 SB_RX2P N AA5 AA6 88 SB_RX3P N W5 Y5 89 LVDS_DIGON E9 90 LVDS_ENA_BL G12 91 LVDS_BLON F...

Page 85: ... clock to the REF_CLKP pin and a 10MHz differential clock pair to the HT_REFCLKP N pins to enable I Os for testing 2 Set POWERGOOD to 0 3 Set TESTMODE to 1 4 Set DAC_SDA to 0 5 Load JTAG instruction register with the instruction 0110 0011 6 Load JTAG instruction register with the instruction 0010 0111 7 Set POWERGOOD to 1 1 6 5 4 3 2 VOH VOL mode TEST_ODD TEST_EVEN Table 7 4 Truth Table for the VO...

Page 86: ...OH VOL Pin List Table 7 5 shows the RS780E VOH VOL tree There is no specific order for connection Under the Control column an ODD or EVEN indicates that the logical output of the pin is same as the TEST_ODD or TEST_EVEN input respectively When a differential pair appear in the table as a single entry the output of the positive P pin is indicated in the Control column see last paragraph for explana...

Page 87: ... Even 26 MEM_DQ7 Y15 Odd 27 MEM_DQ8 AC20 Even 28 MEM_DQ9 AD19 Odd 29 MEM_DQ10 AE22 Even 30 MEM_DQ11 AC18 Odd 31 MEM_DQ12 AB20 Even 32 MEM_DQ13 AD22 Odd 33 MEM_DQ14 AC22 Even 34 MEM_DQ15 AD21 Odd 35 MEM_DM0 W17 Even 36 MEM_DM1 AE19 Odd 37 MEM_DQS0P N Y17 W18 Even 38 MEM_DQS1P N AD20 AE21 Odd 39 MEM_CKE AB18 Even 40 MEM_CS AB13 Odd 41 MEM_ODT V14 Even 42 MEM_WE AD18 Odd 43 MEM_RAS W12 Even 44 MEM_CA...

Page 88: ...P N N2 N1 Even 78 GFX_TX15P N P1 P2 Odd 79 GPP_TX0P N AC1 AC2 Even 80 GPP_TX1P N AB4 AB3 Odd 81 GPP_TX2P N AA2 AA1 Even 82 GPP_TX3P N Y1 Y2 Odd 83 GPP_TX4P N Y4 Y3 Even 84 GPP_TX5P N V1 V2 Odd 85 SB_TX0P N AD7 AE7 Even 86 SB_TX1P N AE6 AD6 Odd 87 SB_TX2P N AB6 AC6 Even 88 SB_TX3P N AD5 AE5 Odd 89 LVDS_BLON F7 Even 90 LVDS_ENA_BL G12 Odd 91 LVDS_DIGON E9 Even 92 DAC_VSYNC B11 Odd 93 DAC_HSYNC A11 E...

Page 89: ... A 1 Appendix A Pin Listings This appendix contains pin listings for the RS780E sorted in different ways To go to the listing of interest use the linked cross references below RS780E Pin List Sorted by Ball Reference on page A 2 RS780E Pin List Sorted by Pin Name on page A 7 ...

Page 90: ... AB14 MEM_A6 AB15 VSS AB16 MEM_A5 AB17 VSS AB18 MEM_CKE AB19 VSS AB2 VSSAPCIE AB20 MEM_DQ12 AB21 VSS AB22 VDDHTTX AB23 HT_RXCLK1P AB24 HT_RXCAD9N AB25 HT_RXCAD9P AB3 GPP_TX1N AB4 GPP_TX1P AB5 VSSAPCIE AB6 SB_TX2P AB7 VSSAPCIE AB8 PCE_CALRN AB9 VDDA18PCIE AC1 GPP_TX0P AC10 VDD_MEM AC12 VSS AC14 MEM_A12 AC16 MEM_A10 AC18 MEM_DQ11 AC2 GPP_TX0N AC20 MEM_DQ8 AC22 MEM_DQ14 AC23 VDDHTTX AC24 HT_RXCAD8P A...

Page 91: ...STAT D13 TESTMODE D14 PLLVDD18 D15 VSSLT D16 TXCLK_UP D17 TXCLK_UN D18 TXOUT_U3P D19 TXOUT_U3N D2 GFX_TX3N D20 TXOUT_U2P D21 TXOUT_U2N D22 VDDHTRX D23 VSSAHT D24 HT_TXCAD0P D25 HT_TXCAD0N D3 VSSAPCIE D4 GFX_RX0P D5 VSSAPCIE D6 VDDPCIE D7 VDDA18PCIEPLL D8 SYSRESET D9 TMDS_HPD E1 GFX_TX4N E11 REFCLK_P E12 AVDD E14 VSS E15 VSS E17 RESERVED E18 GREEN E19 BLUE E2 GFX_TX4P E20 VSSLT E21 VDDHTRX E22 VSSA...

Page 92: ...VDDHT K17 HT_TXCAD11N K2 GFX_TX11N K22 HT_TXCAD7N K23 HT_TXCAD7P K24 HT_TXCAD6P K25 HT_TXCAD6N K3 GFX_TX10N K4 GFX_TX10P K9 VDDPCIE L1 VSSAPCIE L10 VDDA18PCIE L11 VDDC L12 VSS L14 VDDC L15 VSS L16 VDDHT L17 VSSAHT L18 HT_TXCAD13N L19 HT_TXCAD12P L2 VSSAPCIE L20 HT_TXCLK1N L21 HT_TXCLK1P L22 VSSAHT L24 VSSAHT L25 VSSAHT L4 VSSAPCIE L5 GFX_RX8P L6 GFX_RX8N L7 VSSAPCIE L8 GFX_RX9N L9 VDDPCIE M1 GFX_T...

Page 93: ...DDC U14 VSS U15 VSS U16 VDDC U17 VDDHTTX U18 HT_RXCAD15N U19 HT_RXCAD15P U2 GPP_REFCLKN U20 HT_RXCAD14P U21 HT_RXCAD14N U22 VSSAHT U24 HT_RXCAD3P U25 HT_RXCAD3N U4 VSSAPCIE U5 GPP_RX4P U6 GPP_RX4N U7 GPP_RX5N U8 GPP_RX5P U9 VDDPCIE V1 GPP_TX5P V11 MEM_A2 V12 VSS V14 MEM_ODT V15 MEM_CKP V17 MEM_DQ4 V18 VDDHTTX V19 VSSAHT V2 GPP_TX5N V20 HT_RXCAD13N V21 HT_RXCAD13P V22 HT_RXCAD1P V23 HT_RXCAD1N V24 ...

Page 94: ...45732 AMD 780E Databook 3 10 2009 Advanced Micro Devices Inc A 6 Proprietary Pin Listings Y4 GPP_TX4P Y5 SB_RX3N Y6 VSSAPCIE Y7 SB_RX1N Y8 SB_RX0N Y9 VDDA18PCIE Ball Ref Pin Name ...

Page 95: ... GFX_RX8N L6 GFX_RX8P L5 GFX_RX9N L8 GFX_RX9P M8 GFX_TX0N B5 GFX_TX0P A5 GFX_TX10N K3 GFX_TX10P K4 GFX_TX11N K2 GFX_TX11P K1 GFX_TX12N M3 GFX_TX12P M4 GFX_TX13N M2 GFX_TX13P M1 GFX_TX14N N1 GFX_TX14P N2 GFX_TX15N P2 GFX_TX15P P1 GFX_TX1N B4 GFX_TX1P A4 GFX_TX2N B2 GFX_TX2P C3 GFX_TX3N D2 GFX_TX3P D1 GFX_TX4N E1 GFX_TX4P E2 GFX_TX5N F3 GFX_TX5P F4 GFX_TX6N F2 GFX_TX6P F1 GFX_TX7N H3 GFX_TX7P H4 GFX...

Page 96: ...AD2P F24 HT_TXCAD3N F22 HT_TXCAD3P F23 HT_TXCAD4N H22 HT_TXCAD4P H23 HT_TXCAD5N J24 HT_TXCAD5P J25 HT_TXCAD6N K25 HT_TXCAD6P K24 HT_TXCAD7N K22 HT_TXCAD7P K23 HT_TXCAD8N G21 HT_TXCAD8P F21 HT_TXCAD9N H21 HT_TXCAD9P G20 HT_TXCALN B25 HT_TXCALP B24 HT_TXCLK0N H25 HT_TXCLK0P H24 HT_TXCLK1N L20 HT_TXCLK1P L21 HT_TXCTL0N M25 HT_TXCTL0P M24 HT_TXCTL1N R18 HT_TXCTL1P P19 I2C_CLK B9 I2C_DATA A9 IOPLLVDD A...

Page 97: ...9 TXOUT_U0N A18 TXOUT_U0P B18 TXOUT_U1N B17 TXOUT_U1P A17 TXOUT_U2N D21 TXOUT_U2P D20 TXOUT_U3N D19 TXOUT_U3P D18 VDD_MEM AA11 VDD_MEM AB10 VDD_MEM AC10 VDD_MEM AD10 VDD_MEM AE10 VDD_MEM Y11 VDD18 F9 VDD18 G9 VDD18_MEM AD11 VDD18_MEM AE11 VDD33 H11 VDD33 H12 VDDA18HTPLL H17 VDDA18PCIE AA9 VDDA18PCIE AB9 VDDA18PCIE AD9 VDDA18PCIE AE9 VDDA18PCIE H9 VDDA18PCIE J10 VDDA18PCIE K10 VDDA18PCIE L10 VDDA18...

Page 98: ...11 VSS U14 VSS U15 VSS V12 VSS W11 VSS W15 VSS Y18 VSSAHT A25 VSSAHT AD25 VSSAHT D23 VSSAHT E22 VSSAHT G22 VSSAHT G24 VSSAHT G25 VSSAHT H19 VSSAHT H20 VSSAHT J22 VSSAHT L17 VSSAHT L22 VSSAHT L24 VSSAHT L25 VSSAHT M20 VSSAHT N22 VSSAHT P20 VSSAHT R19 VSSAHT R22 VSSAHT R24 VSSAHT R25 VSSAHT U22 VSSAHT V19 VSSAHT W22 Pin Name Ball Ref VSSAHT W24 VSSAHT W25 VSSAHT Y21 VSSAPCIE A2 VSSAPCIE AA4 VSSAPCIE...

Page 99: ...Pin Listings 2009 Advanced Micro Devices Inc 45732 AMD 780E Databook 3 10 Proprietary A 11 VSSLT C16 VSSLT C18 VSSLT C20 VSSLT C22 VSSLT D15 VSSLT E20 VSSLTP18 B13 Pin Name Ball Ref ...

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Page 101: ...v 1 15 July 2009 First release of the public version Rev 1 20 July 2009 Updated Section 1 2 11 DVI HDMI Added support for YCbCr 4 4 4 and 4 2 2 modes Updated Section 1 4 Branding Diagram Corrected part number in the branding Rev 3 10 Aug 2009 Updated book title and cover page with the device s marketing name ...

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