Chapter 2: Quick Start Tutorial
2–11
Procedures
© December 2009 Altera Corporation
TimeQuest Timing Analyzer Quick Start Tutorial
Because additional constraints are applied to the design, create an additional SDC that
contains only the input and output constraints with the text editor (for example,
inout_delay.sdc
). Add the input and output delay assignments shown in
Table 2–23
to the new SDC created in
“Step 10: Save Constraints to an SDC File”
.
All ports should be constrained in the design after you read the SDC containing the
input and output delay constraints.
1
Remember to update the timing netlist after reading the new constraints. For more
information, refer to
“Step 7: Update the Timing Netlist”
.
To verify all ports are constrained in the design, regenerate the Unconstrained Paths
Summary report (
Figure 2–9
).
Generate specific timing check reports for clocks or nodes in the design with the
procedures in
Table 2–24
. The procedures in
Table 2–24
generate a report where
clk
clocks the destination register to the design destination register bus
acc:inst3|result
and reports the top 10 worst paths.
Table 2–23.
Input and Output Delay Assignments
The TimeQuest Timing Analyzer GUI
The TimeQuest Timing Analyzer Console
1. On the Constraints menu, click
Set Input Delay
. The
Set
Input Delay
dialog box appears.
2. Enter the following:
Clock name
: clk
Delay value
: 2
Targets
: [get_ports {d[0] d[1] d[2] d[3] \
d[4] d[5] d[6] d[7] newt reset}]
3. On the Constraints menu, click
Set Output Delay
. The
Set
Output Delay
dialog box appears.
4. Enter the following:
Clock name
: clk
Delay value
: 1.5
Targets
: [get_ports {yn_out[0] yn_out[1] \
yn_out[2] yn_out[3] yn_out[4] yn_out[5] \
yn_out[6] yn_out[7] yvalid follow}]
To constrain the input ports, type:
set_input_delay -clock clk 2 \
[get_ports {d* newt reset}]
r
To constrain the output ports, type:
set_output_delay -clock clk 1.5 \
[get_ports {yn_out* yvalid follow}]
r
Figure 2–9.
Regenerated Unconstrained Paths Summary Report
