2–10
Chapter 2: Quick Start Tutorial
Procedures
TimeQuest Timing Analyzer Quick Start Tutorial
© December 2009 Altera Corporation
After you generate the Summary (Setup) report, generate a clock hold check summary
for the design with the procedures in
Table 2–21
.
Figure 2–7
shows the Summary (Hold) report.
The Summary (Hold) report indicates that the
clk
clock node meets the timing
constraints by 0.661 ns.
Specify all timing constraints and exceptions prior to performing a full compilation
with the procedures in
Table 2–22
. This ensures that the Fitter optimizes for the critical
paths in the design.
You can use the
Report Unconstrained Paths
command to verify that you have
constrained all paths in the
fir_filter
design.
Figure 2–8
shows the Unconstrained Paths Summary report.
The Unconstrained Paths Summary report indicates that there are numerous
unconstrained paths and details the types of paths.
To fully constrain this design, utilize the full set of SDC constraints provided by the
TimeQuest Timing Analyzer.
To fully constrain the
fir_filter
design, constrain all input and output ports. Use the
Set Input Delay
and
Set Output Delay
dialog boxes, or the
set_input_delay
and
set_output_delay
constraints to specify the input and output delay values.
Table 2–21.
Generating the Summary (Hold) Report
TimeQuest Timing Analyzer GUI
TimeQuest Timing Analyzer Console
In the
Tasks
pane, double-click
Report Hold Summary
.
Type:
create_timing_summary –hold
r
Figure 2–7.
Summary (Hold) Report
Table 2–22.
Specifying Timing Constraints and Exceptions
TimeQuest Timing Analyzer GUI
TimeQuest Timing Analyzer Console
In the
Tasks
pane, double-click
Report Unconstrained Paths
. Type:
report_ucp
r
Figure 2–8.
Unconstrained Paths Summary Report
