2–6
Chapter 2: Quick Start Tutorial
Procedures
TimeQuest Timing Analyzer Quick Start Tutorial
© December 2009 Altera Corporation
Figure 2–3
shows the Clock Transfers report.
The Clock Transfers report indicates that a clock-to-clock transfer exists between the
clk
source and the
clkx2
destination. There are 16 instances where
clk
clocks the
source node and where
clkx2
clocks the destination node.
In the
fir_filter
design, you do not have to analyze clock transfers from
clk
to
clkx2
because they are false paths. Declare the paths from
clk
to
clkx2
as false paths with
the procedures in
Table 2–13
. When you complete this procedure, the TimeQuest
Timing Analyzer indicates that the Clock Transfers report is outdated.
1
Alternatively, use the
set_clock_groups
command to declare the paths between
the two clock domains as false paths. For example,
set_clock_groups
-asynchronous -group [get_clocks clk] -group [get_clocks clkx2]
.
This command declares all paths from
clk
to
clkx2
and from
clkx2
to
clk
as false
paths. This method is preferred.
Because you have added a new timing constraint, update the timing netlist with the
procedure in
Table 2–14
.
Table 2–12.
Generating the Report Clock Transfers
TimeQuest Timing Analyzer GUI
TimeQuest Timing Analyzer Console
In the
Tasks
pane, double-click the
Report Clock Transfers
command.
Type:
report_clock_transfers
r
Figure 2–3.
Clock Transfers Report
Table 2–13.
Declaring False Paths
TimeQuest Timing Analyzer GUI
TimeQuest Timing Analyzer Console
1. In the Clock Transfers report, select
clk
in the
From Clock
column.
2. Right-click and select
Set False Paths Between Clock
Domains
. This command declares all paths from
registers clocked by
clk
to registers clocked by
clkx2
as false paths.
Type:
set_false_path -from [get_clocks clk] \
-to [get_clocks clkx2]
r
Table 2–14.
Updating the Timing Netlist
TimeQuest Timing Analyzer GUI
TimeQuest Timing Analyzer Console
In the
Tasks
pane, double-click the
Update Timing Netlist
command.
Type:
update_timing_netlist
r
