101 Innovation DriveSan Jose, CA 95134
www.altera.com
TimeQuest Timing Analyzer
Quick Start Tutorial
Software Version:
9.1
Document Version:
1.1
Document Date:
© December 2009
UG-TMQSTANZR-1.1
Page 1: ...101 Innovation Drive San Jose CA 95134 www altera com TimeQuest Timing Analyzer Quick Start Tutorial Software Version 9 1 Document Version 1 1 Document Date December 2009 UG TMQSTANZR 1 1...
Page 2: ...patents and pending ap plications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but...
Page 3: ...zer 2 2 Step 5 Create a Post Map Timing Netlist 2 3 Step 6 Specify Timing Requirements 2 3 Step 7 Update the Timing Netlist 2 4 Step 8 Save the Synopsys Design Constraints SDC File 2 4 Step 9 Generate...
Page 4: ...iv TimeQuest Timing Analyzer Quick Start Tutorial December 2009 Altera Corporation...
Page 5: ...torial This tutorial describes the steps to constrain and perform static timing analysis with the TimeQuest Timing Analyzer For this tutorial use the fir_filter design that ships with the Quartus II s...
Page 6: ...1 2 Chapter 1 About this Tutorial TimeQuest Timing Analyzer Quick Start Tutorial December 2009 Altera Corporation...
Page 7: ...GUI or the command line equivalent procedures in Table 2 1 Step 2 Setup the TimeQuest Timing Analyzer By default the Quartus II software uses the Classic Timing Analyzer as the timing analysis tool f...
Page 8: ...y opened If you use the GUI select No when the following message appears No SDC files were found in the Quartus Settings File and filtref sdc doesn t exist Would you like to generate an SDC file from...
Page 9: ...supported by the TimeQuest Timing Analyzer refer to the TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook 1 By default the create_clock command assumes a 50 50 duty cycle if th...
Page 10: ...cally saved 1 If you inadvertently overwrite any of your constraints later in the design flow use this initial SDC file to restore all of your constraints The initial SDC file can act as the golden SD...
Page 11: ...onstraints and exceptions specified in the design Two reports are generated one for the clocks and one for the clock groups Generate a report that summarizes all clocks in the design with the procedur...
Page 12: ...s clk group get_clocks clkx2 This command declares all paths from clk to clkx2 and from clkx2 to clk as false paths This method is preferred Because you have added a new timing constraint update the t...
Page 13: ...e procedures in Table 2 15 Figure 2 4 shows the new SDC Assignments report The report shown in Figure 2 4 indicates that the clock constraints and the false paths are correct Use the Report Clocks and...
Page 14: ...yzer To obtain detailed timing analysis data on specific paths view timing analysis results in the TimeQuest Timing Analyzer 1 After a full place and route is performed launch the TimeQuest Timing Ana...
Page 15: ...kx2 The Slack column in the Summary Setup report indicates that clk fails to meet the constraint by 11 588 ns The End Point TNS column is the total of all total negative slack TNS for the specified cl...
Page 16: ...ummary report The Unconstrained Paths Summary report indicates that there are numerous unconstrained paths and details the types of paths To fully constrain this design utilize the full set of SDC con...
Page 17: ...locks or nodes in the design with the procedures in Table 2 24 The procedures in Table 2 24 generate a report where clk clocks the destination register to the design destination register bus acc inst3...
Page 18: ...ter to optimize the design based on your new constraints or exceptions Multiple iterations on the design may be necessary to achieve the desired results Table 2 24 Generate a Report Timing Report Time...
Page 19: ...g analysis tool 1 The Classic Timing Analyzer is the default timing analyzer in the Quartus II software Example 3 3 shows the content of the main_postmap tcl script Use this script to create post map...
Page 20: ...the flow package to create a post map netlist package require quartus flow r open the project in TimeQuest project_open filtref r create a post map database execute_module tool map r create the timing...
Page 21: ...e_timing_netlist r report unconstrained paths report_clocks r create_timing_summary setup r create_timing_summary hold r create_timing_summary recovery r create_timing_summary removal r report_ucp r d...
Page 22: ...3 4 Chapter 3 Script Examples Commands and Tcl Scripts TimeQuest Timing Analyzer Quick Start Tutorial December 2009 Altera Corporation...
Page 23: ...ion altera com Note 1 You can also contact your local Altera sales office or sales representative Visual Cue Meaning Bold Type with Initial Capital Let ters Command names dialog box titles checkbox op...
Page 24: ...the AHDL keyword SUBDE SIGN as well as logic function names e g TRI are shown in Courier 1 2 3 and a b c etc Numbered steps are used in a list of items when the sequence of the items is impor tant suc...
