Altera DE2 Board Page 66 Getting Started Manual Download

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Lab 6: Ethernet Packet Sending/Receiving

Figure 10.1 Packet Sending and Receiving using NIOS II CPU

10-2

Lab Setup and Instructions

Project Directory: C:\DE2\UP4_NET

Bitstream Used: UP4_API.sof or UP4_API.pof

NIOSII Workspace: C:\DE2\UP4_NET

Refer to Figure 10.2 and setup the lab according to the following steps:

Plug in a CAT5 loopback cable into the Ethernet connector of DE2.

Load the bitstream into FPGA

Run NIOSII IDE under the workspace C:\DE2\UP4_NET

Click on “Compile and Run” button

Now you can observed the content of the packets received (64-byte packets

sent, 68-byte packets received because of the extra checksum bytes).

Summary of Contents for DE2 Board

Page 1: ...Altera DE2 Board Development and Education Board Getting Started Guide DE2 Board Document Version 1 2 OCT 02 2005 by Terasic Preliminary Version 2005 by Altera...

Page 2: ...USING THE LEDS AND SWITCHES 18 3 7 USING THE 7 SEG DISPLAYS AND LCD MODULE 21 3 8 USING THE EXPANSION HEADERS 24 3 9 USING THE SERIAL PORTS RS232 26 3 10 USING THE SERIAL PORTS PS 2 27 3 11 USING THE...

Page 3: ...ND INSTRUCTIONS 33 CHAPTER 11 LAB 7 DE2 CONTROL PANEL 33 11 1 LAB SETUP AND INSTRUCTIONS 33 11 2 CONTROL THE BOARD USING DE2 CONTROL PANEL 33 11 3 THE FLASH PROGRAMMER 33 11 4 THE SDRAM SRAM CONTROLLE...

Page 4: ...pter provides users key information about the kit 1 1Kit Contents Figure 1 1 shows the photo of the DE2 package The DE2 Kit includes The DE2 Board USB Cable for FPGA programming and control DE2 Lab CD...

Page 5: ...ched bag of copper stands silicon feet cover and screw to create suitable feet according to users s own applications Assemble a screw a copper stand and a rubber silicon cover as shown in Figure 1 2 f...

Page 6: ...t the Kit 3 Figure 1 2 The Rubber Feet Set 1 3Getting Help Here are some places to get help if you encounter any problem Email to support terasic com Taiwan China 886 3 550 8800 Korea Japan 82 2 512 7...

Page 7: ...arranged so that they are properly aligned This nice alignment will increase the yield for manufacturing and ease board debugging procedure Jumper free design for robustness Jumpers are a great point...

Page 8: ...D and MP3 players The DE2 platform allows users to quickly understand all the insight tricks to design real multimedia projects for industry Altera Cyclone II 2C35 FPGA with 35000 LEs Altera Serial Co...

Page 9: ...B connectors RS 232 Transceiver and 9 pin connector PS 2 mouse keyboard connector IrDA transceiver Two 40 pin Expansion Headers with diode protection DE2 Lab CD ROM which contains many examples with...

Page 10: ...ode are supported Provides EPCS16 Serial Configuration device 8Mbyte SDRAM Single Data Rate Synchronous Dynamic RAM memory chip Organized as 1M x 4 x 16 bit Support access through both NIOS II and Ter...

Page 11: ...nes XSGA DAC Output Uses ADI 7123 240Mhz Triple 10 bit High speed Video DAC With 15 pin high density D sub connector Supports up to 1600x1200 at 100Hz refresh rate best performance and quality provide...

Page 12: ...One type A for host and one type B for device on DE2 Provides high speed parallel interface to most CPUs available Supports NIOS II Core with driver now implemented by Terasic Supports Programmed I O...

Page 13: ...nitor to your DE2 4 Connect your headset to your DE2 5 Press the Power ON OFF Switch on DE2 6 Make sure the RUN PROG switch is set to RUN position Note that PROG position is only used for AS Mode prog...

Page 14: ...Altera DE2 Board 11 board Your voice will be mixed with the music played from the MP3 player Figure 2 3 The default VGA Output Pattern...

Page 15: ...JTAG mode Figure 3 1 describes the block diagram of the JTAG programming method Follow the steps below to program the FPGA Ensure the 9V power is supplied to the DE2 Board Connect USB Cable to the USB...

Page 16: ...a PC Set the switch to PROG for AS mode Note that the switch position should be kept at RUN position for normal operation Figure 3 3 shows the AS mode connection scheme Perform the following steps to...

Page 17: ...of the three links at any given time Figure 3 4 The Terasic Link is used to allow the software in PC side to communicate with the API IP core inside the FPGA 3 4XSGA Output ADV7123 from Analog Devices...

Page 18: ...0 c SVGA 60Hz 800x600 3 2 2 2 20 1 40 800 c SVGA 75Hz 800x600 1 6 3 2 16 2 0 3 49 800 c SVGA 85Hz 800x600 1 1 2 7 14 2 0 6 56 800 c XGA 60Hz 1024x768 2 1 2 5 15 8 0 4 65 1024 c XGA 70Hz 1024x768 1 8 1...

Page 19: ...VGA Green 3 VGA_G 4 PIN_B10 VGA Green 4 VGA_G 5 PIN_A10 VGA Green 5 VGA_G 6 PIN_G11 VGA Green 6 VGA_G 7 PIN_D11 VGA Green 7 VGA_G 8 PIN_E12 VGA Green 8 VGA_G 9 PIN_D12 VGA Green 9 VGA_B 0 PIN_J13 VGA...

Page 20: ...under C DE2 Datasheet Audio CODEC Figure 3 7 shows the circuit diagram of the audio part of DE2 The pin assignment of the associated interface is shown in Table 3 2 Figure 3 7 24 bit Audio DAC Signal...

Page 21: ...push button is pressed only one zero pulse will be generated There are also 18 toggle switches on the DE2 boards for users to set HIGH LOW to the 18 GPIOs of the CycloneII FPGA The DE2 Board has 9 gr...

Page 22: ...AF14 DPDT Switch 4 SW 5 PIN_AD13 DPDT Switch 5 SW 6 PIN_AC13 DPDT Switch 6 SW 7 PIN_C13 DPDT Switch 7 SW 8 PIN_B13 DPDT Switch 8 SW 9 PIN_A13 DPDT Switch 9 SW 10 PIN_N1 DPDT Switch 10 SW 11 PIN_P1 DPD...

Page 23: ...DR 6 PIN_AD21 LED Red 6 LEDR 7 PIN_AC21 LED Red 7 LEDR 8 PIN_AA14 LED Red 8 LEDR 9 PIN_Y13 LED Red 9 LEDR 10 PIN_AA13 LED Red 10 LEDR 11 PIN_AC14 LED Red 11 LEDR 12 PIN_AD15 LED Red 12 LEDR 13 PIN_AE1...

Page 24: ...signals according to its specific timing to display desired characters at the correct location For detailed information on how to use the LCD module users can refer to the spec under C DE2 Datasheet L...

Page 25: ...N_V22 Seven Segment Digital 2 1 HEX2 2 PIN_AC25 Seven Segment Digital 2 2 HEX2 3 PIN_AC26 Seven Segment Digital 2 3 HEX2 4 PIN_AB26 Seven Segment Digital 2 4 HEX2 5 PIN_AB25 Seven Segment Digital 2 5...

Page 26: ...Digital 7 1 HEX7 2 PIN_L9 Seven Segment Digital 7 2 HEX7 3 PIN_L6 Seven Segment Digital 7 3 HEX7 4 PIN_L7 Seven Segment Digital 7 4 HEX7 5 PIN_P9 Seven Segment Digital 7 5 HEX7 6 PIN_N9 Seven Segment...

Page 27: ...e related schematics The pin assignment of the associated interface is shown in Table 3 8 Figure 3 10 Two 40 pin Expansion Headers Signal Name FPGA Pin No Description GPIO_0 0 PIN_D25 GPIO Connection...

Page 28: ...GPIO_0 24 PIN_K19 GPIO Connection 0 24 GPIO_0 25 PIN_K21 GPIO Connection 0 25 GPIO_0 26 PIN_K23 GPIO Connection 0 26 GPIO_0 27 PIN_K24 GPIO Connection 0 27 GPIO_0 28 PIN_L21 GPIO Connection 0 28 GPIO...

Page 29: ...ction 1 25 GPIO_1 26 PIN_R19 GPIO Connection 1 26 GPIO_1 27 PIN_T19 GPIO Connection 1 27 GPIO_1 28 PIN_U20 GPIO Connection 1 28 GPIO_1 29 PIN_U21 GPIO Connection 1 29 GPIO_1 30 PIN_V26 GPIO Connection...

Page 30: ...face with a connector for a PS 2 keyboard or mouse Figure 3 12 shows the schematic of the PS 2 connector and circuits For how to use PS 2 mouse and keyboards users can refer to http www computer engin...

Page 31: ...design for the Fast Ethernet interface for DE2 The pin assignment of the associated interface is shown in Table 3 11 Figure 3 13 Fast Ethernet Solution for DE2 Signal Name FPGA Pin No Description ENE...

Page 32: ...integrated video decoder automatically detects and converts a standard analog baseband televison signal compatible with worldwide standards NTSC PAL and SECAM into 4 2 2 component video data compatib...

Page 33: ...der Data 2 TD_DATA 3 PIN_H10 TV Decoder Data 3 TD_DATA 4 PIN_G9 TV Decoder Data 4 TD_DATA 5 PIN_F9 TV Decoder Data 5 TD_DATA 6 PIN_D7 TV Decoder Data 6 TD_DATA 7 PIN_C7 TV Decoder Data 7 TD_HS PIN_D5...

Page 34: ...using Philips ISP1362 single chip USB controller The host and device controllers are compliant with Universal Serial Bus Specification Rev 2 0 supporting data transfer at full speed 12Mbit s and low s...

Page 35: ...OTG_DATA 3 PIN_F7 ISP1362 Data 3 OTG_DATA 4 PIN_J5 ISP1362 Data 4 OTG_DATA 5 PIN_J8 ISP1362 Data 5 OTG_DATA 6 PIN_J7 ISP1362 Data 6 OTG_DATA 7 PIN_H6 ISP1362 Data 7 OTG_DATA 8 PIN_E2 ISP1362 Data 8 O...

Page 36: ...P1362 3 15Using IrDA The DE2 Board also provides a simple wireless communication media using a 115 2Kb s Low Power Infrared Transceiver Please refer to the specification in C DE2 DataSheet IrDA for de...

Page 37: ...gnment for IrDA 3 16Using SDRAM SRAM Flash Figure 3 16 shows the schematic of SDRAM SRAM and Flash Memory The DE2 Board provides 8Mbyte SDRAM 512KByte SRAM and 1Mbyte Flash Memory Figure 3 17 shows th...

Page 38: ...AM_ADDR 7 PIN_U5 SDRAM Address 7 DRAM_ADDR 8 PIN_W4 SDRAM Address 8 DRAM_ADDR 9 PIN_W3 SDRAM Address 9 DRAM_ADDR 10 PIN_Y1 SDRAM Address 10 DRAM_ADDR 11 PIN_V5 SDRAM Address 11 DRAM_DQ 0 PIN_V6 SDRAM...

Page 39: ...Assignment for SDRAM Signal Name FPGA Pin No Description SRAM_ADDR 0 PIN_AE4 SRAM Address 0 SRAM_ADDR 1 PIN_AF4 SRAM Address 1 SRAM_ADDR 2 PIN_AC5 SRAM Address 2 SRAM_ADDR 3 PIN_AC6 SRAM Address 3 SRA...

Page 40: ...ble SRAM_UB_N PIN_AF9 SRAM High byte Data Mask SRAM_LB_N PIN_AE9 SRAM Low byte Data Mask SRAM_CE_N PIN_AC11 SRAM Chip Enable Table 3 16 Pin Assignment for SRAM Signal Name FPGA Pin No Description FL_A...

Page 41: ...DQ 0 PIN_AD19 FLASH Data 0 FL_DQ 1 PIN_AC19 FLASH Data 1 FL_DQ 2 PIN_AF20 FLASH Data 2 FL_DQ 3 PIN_AE20 FLASH Data 3 FL_DQ 4 PIN_AB20 FLASH Data 4 FL_DQ 5 PIN_AC20 FLASH Data 5 FL_DQ 6 PIN_AF21 FLASH...

Page 42: ...he QuartusII CD ROM in the kit Log on to the Altera web site at www altera com licensing Click Quartus II Web Edition Software and follow the instructions to request your license A license file is e m...

Page 43: ...nue Anyway if there is any warning message Click Finish and reboot your PC to complete the process 4 3Potential Problems and Workaround for Using USB Blaster Problems may occur when you remove the USB...

Page 44: ...all the labs and API software into your C DE2 If you encounter the picture shown in Figure 4 2 Simply click on Ignore to continue After the installation is complete you can access DE2 s lab examples...

Page 45: ...and Pin Assignment The complete top level pin assignment is provided in C DE2 DE2_TOP project Please use the pin assignment in DE2_TOP project as golden pin assignment for all your projects The top l...

Page 46: ...pile and load the default bitstream into the DE2 Board 5 1Power Up the Board Connect your USB download cable and power supply to the DE2 board Push the Power ON OFF button on the board The Power LED w...

Page 47: ...each pin in the top level module DE2 Top Level Pin Definition module DE2_Default Clock Input CLOCK_27 27 MHz CLOCK_50 50 MHz EXT_CLOCK External Clock Push Button KEY Button 3 0 DPDT Switch SW DPDT Swi...

Page 48: ...FL_ADDR FLASH Address bus 20 Bits FL_WE_N FLASH Write Enable FL_RST_N FLASH Reset FL_OE_N FLASH Output Enable FL_CE_N FLASH Chip Enable SRAM Interface SRAM_DQ SRAM Data bus 16 Bits SRAM_ADDR SRAM Addr...

Page 49: ...d LCD_EN LCD Enable LCD_RS LCD Command Data Select 0 Command 1 Data LCD_DATA LCD Data bus 8 bits SD_Card Interface SD_DAT SD Card Data SD_DAT3 SD Card Data 3 SD_CMD SD Card Command Signal SD_CLK SD Ca...

Page 50: ...ET_INT DM9000A Interrupt ENET_CLK DM9000A Clock 25 MHz Audio CODEC AUD_ADCLRCK Audio CODEC ADC LR Clock AUD_ADCDAT Audio CODEC ADC Data AUD_DACLRCK Audio CODEC DAC LR Clock AUD_DACDAT Audio CODEC DAC...

Page 51: ...ert programming file to POF format Figure 5 3 shows the Convert Programming File menu Figure 5 3 Open the menu for Converting Programming Files 2 In the Convert Programming Files Menu Select EPCS16 as...

Page 52: ...design is finalized or the design has to be tested without a PC Set the switch to PROG for AS mode Note that the switch position should be kept at RUN position for normal operation Perform the followi...

Page 53: ...on off so that the FPGA can load the bitstream from the Serial Configuration Device Note The first time when you open up a Quartus II design project copied from somewhere else and open the Programmin...

Page 54: ...k which is using I2C protocol to communicate with the TV Decoder chip After power on sequence the TV Decoder chip will have an unstable period Lock detector is responsible for detecting this unstable...

Page 55: ...DE2_TV pof Refer to Figure 6 2 and setup the lab according to the following steps Connect a DVD player s Video output to the Video IN RCA Jack of the DE2 board Connect the VGA output of the DE2 board...

Page 56: ...Lab 2 TV Box 53 Figure 6 2 The Lab Setup for TV Box Important Note for the Lab DVD Player must set to the following mode 1 NTSC 2 60Hz 3 4 3 ratio 4 Non progressive mode...

Page 57: ...controller IP to perform the real time image storage and display Figure 7 1 illustrates the block diagram of the design where users can draw lines on the screen using a USB mouse The VGA Controller IP...

Page 58: ...ccording to the following steps Connect a USB Mouse to the USB Host Connector of the DE2 board Connect VGA output to a LCD CRT Monitor Load the bitstream into FPGA Run NIOS II IDE and choose C DE2 UP4...

Page 59: ...Lab 3 USB Paint Brush 56 Figure 7 2 The Lab Setup for USB Paint Brush Application...

Page 60: ...ilips ISP1362 chip Once the software program is successfully executed the PC will find the new device in its USB device list and ask for the associated driver Philips PDIUSBD12 SMART Evaluation Board...

Page 61: ...ing to the following steps Load the bitstream into FPGA Run NIOSII IDE with DE2_ISP_1362_DC as workspace Click on Compile and Run in NIOSII IDE Connect the USB Device connector of the DE2 board to you...

Page 62: ...1362DcUsb exe Click on ADD button to increment the number register shown on the 7 SEG displays The incremented result is also sent back to PC side using the USB link Click on Clear button to clear the...

Page 63: ...ial bit clock BCK and the left right channel clock LRCK automatically Therefore users simply need to configure the sample rate and gain of the audio CODEC The data input from line in is then mixed wit...

Page 64: ...pink color of the DE2 board Connect a MP3 IPOD PC audio output to the LINEIN connector blue color of the DE2 board Connect a headset speaker to the LINEOUT connector green color of the DE2 Load the bi...

Page 65: ...ect two DE2 boards to implement this project In the transmitting side NIOS II CPU sends out a 64 byte packet every 0 5sec to the DM9000A After receiving the packet DM9000A appends the 4 byte checksum...

Page 66: ...I Workspace C DE2 UP4_NET Refer to Figure 10 2 and setup the lab according to the following steps Plug in a CAT5 loopback cable into the Ethernet connector of DE2 Load the bitstream into FPGA Run NIOS...

Page 67: ...Lab 6 Ethernet Packet Sending Receiving 64 Figure 10 2 The Lab Setup for Ethernet Lab...

Page 68: ...USB Blaster link from Quartus II 3 If concurrent debugging using DE2 Control Panel and Altera Signal Tap is desired users should use the DE2 Control Panel s RS232 Version 11 1Lab Setup and Instructio...

Page 69: ...t worrying about how to build a Flash Memory Programmer Perform the following steps to repeat the experiments 1 Figure 6 1 shows the concept of the DE2 Control Panel Users use Window GUI to issue comm...

Page 70: ...page Click on the check boxes of LEDs and click on Set The corresponding LEDs are lighted up Also you can key in text in LCD input window and click on Set The LCD display on the board will change acco...

Page 71: ...Click on Button Flash to change to Flash Memory Control Page Refer to Figure 11 4 Figure 11 4 Flash Memory Control Page 2 Click on Chip Erase The button and window frame title will prompt you to wait...

Page 72: ...lash memory 7 Please load c DE2 Binary_Raw_Data cdda1m into your Flash Memory now so that we can proceed with the Flash Music Player Lab in the next section Figure 11 6 Write an entire file into the F...

Page 73: ...k on Read The rDATA will display the data read back from the address specified 4 You can also load a file into SDRAM by using Sequential Write function Please refer to Figure 11 8 You have to specify...

Page 74: ...he keyboard will be displayed in the message box of the DE2 Control Panel DE2 Control Panel also allows users to control the 7 SEG displays on DE2 Figure 11 9 shows the setup of the connection Figure...

Page 75: ...ores without requiring them to implement complex API Host control software and memory SRAM SDRAM Flash controllers we provide users an integrated control environment consisting of software controller...

Page 76: ...s illustrated in Figure 11 12 select the Asynchronous 1 for Flash Multiplexer and then click on the Configure button to activate the port Note that you need to click the Configure button to enable the...

Page 77: ...sure the checkboxes of Default Image and Cursor Enable are checked Connect your VGA monitor to the DE2 board and you should see the default image shown on the VGA screen with a green cursor which can...

Page 78: ...mage DE2 Control Panel can display users own images on VGA monitors Repeat the following steps to display users own picture on a VGA monitor Switch to SRAM Control Page and load the file C DE2 Binary_...

Page 79: ...or Switch to VGA Page and deselect the checkbox of Default Image You should see the VGA monitor connected to the DE2 board is showing the Raw_Data_Gray stored in SRAM as shown in Figure 11 15 Users ca...

Page 80: ...e window shown in Figure 11 16 should appear Figure 11 16 The Image Converter for converting image into the format for DE2 Control Panel Memory Loading Click on Open Bitmap button and select the 640x4...

Page 81: ...Raw_Data_Gray Color Picture R G B optional BW Threshold Raw_Data_BW Raw_Data_BW txt Grayscale Picture N A N A Raw_Data_Gray Grayscale Picture N A BW Threshold Raw_Data_BW Raw_Data_BW txt Note Raw_Dat...

Page 82: ...NIOS II CPU to read the music data stored in SD Card and use audio CODEC to play the music The audio CODEC is configured in the slave mode where users must provide their own AD DA serial bit clock BCK...

Page 83: ...rmat your SD card into FAT16 format Copy as many as music files in WAV format to be played and store into the SD card if users want to delete a song from the SD card you need to reformat the entire SD...

Page 84: ...Lab 8 SD Card Music Player 81 Figure 12 2 The Lab Setup for SD Card Music Player Lab...

Page 85: ...Demo OCT 02 2005 Sean Peng Release ready for first DE2 production lot 13 2Schematic Please send email to support terasic com for requesting schematic information 13 3Always Visit DE2 Webpage for New L...

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