Using the System
31
3-13
Implementing a TV Encoder
Though the DE2 Board does not have a TV Encoder, the high-end ADV7123
(10-bit high-speed triple ADCs) can be used to implement a professional TV
Encoder with the digital processing part implemented by RTL code in the FPGA.
Figure 3.15 shows the block diagram of a TV Encoder implemented using the
ADV7123 and the FPGA.
Figure 3.14 A TV Encoder diagram implemented by 2F35 and the high-speed
VGA DEC.
3-14
Using USB Host/Device
The DE2 Board provides both USB Host and Device interfaces using Philips
ISP1362 single-chip USB controller. The host and device controllers are
compliant with Universal Serial Bus Specification Rev. 2.0, supporting data
transfer at full-speed (12Mbit/s) and low-speed (1.5Mbit/s).
Please refer to the USB part of DE2 schematic and the specification under
C:\DE2\Datasheet\USB for detail information. The challenge part of designing a
USB application is in the driver side. We provided two completed USB demo
cases in both host and device applications for users to learn how to work with the
ISP1362 under Altera NIOS II core. Please refer to Chapter 7 and Chapter 8 for
details. Figure 3.15 shows the block diagram of the USB part. The pin assignment
of the associated interface is shown in Table 3.13.
