First Lab: DE2 Top-Level and Default Bitstream
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OTG_INT1,
//
ISP1362 Interrupt 1
OTG_DREQ0,
//
ISP1362 DMA Request 0
OTG_DREQ1,
//
ISP1362 DMA Request 1
OTG_DACK0_N,
//
ISP1362 DMA Acknowledge 0
OTG_DACK1_N,
//
ISP1362 DMA Acknowledge 1
//////////////////// LCD Module 16X2
////////////////
LCD_ON,
//
LCD Power ON/OFF
LCD_BLON,
//
LCD Back Light ON/OFF
LCD_RW,
//
LCD Read/Write Select,
// 0 = Write, 1 = Read
LCD_EN,
//
LCD Enable
LCD_RS,
//
LCD Command/Data Select,
// 0 = Command, 1 = Data
LCD_DATA,
//
LCD Data bus 8 bits
//////////////////// SD_Card Interface ////////////////
SD_DAT,
//
SD Card Data
SD_DAT3,
//
SD Card Data 3
SD_CMD,
//
SD Card Command Signal
SD_CLK,
//
SD Card Clock
//////////////////// USB JTAG link
////////////////////
TDI,
// Terasic API Link:
// CPLD -> FPGA (data in)
TCK,
// Terasic API Link:
// CPLD -> FPGA (clock)
TCS,
// Terasic API Link:
// CPLD -> FPGA (CS)
TDO,
// Terasic API Link:
// FPGA -> CPLD (data out)
//////////////////// I2C
////////////////////////////
I2C_SDAT,
//
I2C Data
I2C_SCLK,
//
I2C Clock
//////////////////// PS2
////////////////////////////
PS2_DAT,
//
PS2 Data
PS2_CLK,
//
PS2 Clock
//////////////////// VGA
////////////////////////////
VGA_CLK,
//
VGA Clock
VGA_HS,
//
VGA H_SYNC
VGA_VS,
//
VGA V_SYNC
VGA_BLANK,
//
VGA BLANK
