Using the System
23
HEX5[2]
PIN_P7
Seven Segment Digital 5[2]
HEX5[3]
PIN_T9
Seven Segment Digital 5[3]
HEX5[4]
PIN_R5
Seven Segment Digital 5[4]
HEX5[5]
PIN_R4
Seven Segment Digital 5[5]
HEX5[6]
PIN_R3
Seven Segment Digital 5[6]
HEX6[0]
PIN_R2
Seven Segment Digital 6[0]
HEX6[1]
PIN_P4
Seven Segment Digital 6[1]
HEX6[2]
PIN_P3
Seven Segment Digital 6[2]
HEX6[3]
PIN_M2
Seven Segment Digital 6[3]
HEX6[4]
PIN_M3
Seven Segment Digital 6[4]
HEX6[5]
PIN_M5
Seven Segment Digital 6[5]
HEX6[6]
PIN_M4
Seven Segment Digital 6[6]
HEX7[0]
PIN_L3
Seven Segment Digital 7[0]
HEX7[1]
PIN_L2
Seven Segment Digital 7[1]
HEX7[2]
PIN_L9
Seven Segment Digital 7[2]
HEX7[3]
PIN_L6
Seven Segment Digital 7[3]
HEX7[4]
PIN_L7
Seven Segment Digital 7[4]
HEX7[5]
PIN_P9
Seven Segment Digital 7[5]
HEX7[6]
PIN_N9
Seven Segment Digital 7[6]
Table 3.6 Pin Assignment for 7-SEG Display
Signal Name
FPGA Pin No.
Description
LCD_DATA[0]
PIN_J1
LCD Data[0]
LCD_DATA[1]
PIN_J2
LCD Data[1]
LCD_DATA[2]
PIN_H1
LCD Data[2]
LCD_DATA[3]
PIN_H2
LCD Data[3]
LCD_DATA[4]
PIN_J4
LCD Data[4]
LCD_DATA[5]
PIN_J3
LCD Data[5]
LCD_DATA[6]
PIN_H4
LCD Data[6]
LCD_DATA[7]
PIN_H3
LCD Data[7]
LCD_RW
PIN_K4
LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN
PIN_K3
LCD Enable
LCD_RS
PIN_K1
LCD Command/Data Select, 0 = Command, 1 = Data
LCD_ON
PIN_L4
LCD Power ON/OFF
LCD_BLON
PIN_K2
LCD Back Light ON/OFF
Table 3.7 Pin Assignment for 16x2 LCD Module
