ADM-XRC-5T2-ADV User Manual
ADM-XRC-5T2-ADV User Manual
4.6.2. I/O Bank Voltages
Bank Voltage
Description
0 3.3V
Configuration
I/F
1, 4, 5, 6
1.5V
DDRII SRAM
2
3.3V
SelectMAP I/F, Serial Flash
3 3.3V
Clocks
19, 21, 23, 25
1.8V
DDRII DRAM
27, 29, 31, 33
1.8V
DDRII DRAM (LX330T only)
18
2.5V or 3.3V
Pn4 Interface
11, 13, 15, 17, 26
3.3V
ADV212 Interface
12, 20, 24
1.8V
Local Bus
Table 4 User FPGA I/O Bank Voltages
4.6.3. Memory Interfaces
The ADM-XRC-5T2-ADV has four independent banks of DDRII SDRAM when fitted with a
LX330T, SX240T or FX200T target FPGA. (Two banks with all smaller FPGAs) Each bank
consists of two memory devices in parallel to provide a 32 bit datapath. 1Gb Micron
MT47H64M16 devices are fitted as standard to provide 256MB per bank. The board will
support higher capacity devices when they become available.
The ADM-XRC-5T2-ADV has been designed for compatibility with Xilinx memory interface
cores.
Details of the signalling standards are given in the table below:
Name Direction
I/O
Standard
DDR_ad[15:0],
DDR_ba[2:0],
DDR_rasn,
DDR_casn,
DDR_wen,
DDR_csn,
DDR_cke,
DDR_odt
Output SSTL18_I_DCI
DDR_ck0,
DDR_ckn0
Output DIFF_SSTL18_II
DDR_dq[15:0] BiDir
SSTL18_II
DDR_dm[1:0] Output
SSTL18_II_DCI
DDR_dqs[1:0],
DDR_dqsn[1:0]
BiDir DIFF_SSTL18_II
DDR_ck1,
DDR_ckn1
Output DIFF_SSTL18_II
DDR_dq[31:16] BiDir
SSTL18_II
DDR_dm[3:2] Output
SSTL18_II_DCI
DDR_dqs[3:2],
DDR_dqsn[3:2]
BiDir DIFF_SSTL18_II
Table 5 DDR Memory Bank Configuration
Version 1.0
Page 10
