Alpha Data ADM-PCIE-8K5-FH, User Manual

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ADM-PCIE-8K5-FH User Manual
series. Take care to supply a safe clock in on these signals. See Xilinx UG576 for more details acceptable on
GTH reference clocks.
SI5328_REFCLK_OUT1 comes from the onboard jitter attenuator which can feedback a recovered clock from
the GTH channel for particular standards. The Jitter Attenuator is not fitted by default and requires a custom bulid
option. Contact sales@alpha-data.com for more details.
Signal Target FPGA Input I/O Standard "P" pin "N" pin
SI5328_REFCLK_OUT1 MGTREFCLK0_231 LVDS K10 K9
PCIE_REFCLK_1 MGTREFCLK1_231 LVDS H10 H9
GTH_CLK_2 MGTREFCLK0_232 LVDS F10 F9
EXT_CLK MGTREFCLK1_232 User D10 D9
Table 9 : FireFly Reference Clocks
3.2.6 DDR4 SDRAM Reference Clocks
The two banks of DDR4 SDRAM memory each require a separate reference clock, as per Xilinx UltraScale MIG
design guidelines. The reference clocks for these interfaces are detailed below:
Both clocks are 300MHz by default.
Signal Target FPGA Input I/O Standard "P" pin "N" pin
MEM_CLK_0 IO_L11_T1U_GC_66
DIFF_HSTL_I_12
(or SSTL)
G16 G15
MEM_CLK_1 IO_L11_T1U_GC_44
DIFF_HSTL_I_12
(or SSTL)
AM22 AN22
Table 10 : Memory Reference Clocks
3.3 PCI Express
The ADM-PCIE-8K5-FH is capable of PCIe Gen 1/2/3 with 1/2/4/8 lanes. The FPGA drives these lanes directly
using the Integrated PCI Express block from Xilinx. Negotiation of PCIe link speed and number of lanes used is
generally automatic and does not require user intervention.
PCI Express reset (PERST#) connected to the FPGA at both pins AE15 and AM15.
The other pin assignments for the high speed lanes are provided in the pinout attached to the Complete Pinout
Table
Note:
Different motherboards/backplanes will benefit from different RX equalization schemes within the PCIe IP core
provided by Xilinx. Alpha Data recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the mode to "Advanced" and open the
"GT Settings" tab, change the "form factor driven insertion loss adjustment" from "Add-in Card" to
"Chip-to-Chip" (See Xilinx PG239 for more details).
Page 9 Functional Description
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