ZYNQ Ultr FPGA Board AXU5EV-P User Manual
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The functions of each power distribution are shown in the following table:
Power
Function
+5.0V
USB power supply
+1.8V
Ethernet, USB2.0, BANK66 of Core Board
+3.3V
Ethernet, USB2.0, SD, DP, CAN, RS485
+1.2V
BANK65 of Core Board
Part 3.23: ALINX Customized Fan
Because AXU5EV-P generates a lot of heat when it works normally, we
add a heat sink and fan to the chip on the board to prevent the chip from
overheating. The control of the fan is controlled by the ZYNQ chip. The control
pin is connected to the IO of the BANK44 (AG14). If the IO level output is high,
the MOSFET is turned on and the fan is working. If the IO level output is low,
the fan stops. The fan design on the board is shown in Figure 3-23-1.
Figure 3-23-1
：
Fan Design Schematic
The fan has been screwed to the FPGA development board before leaving
the factory. The power of the fan is connected to the socket of J42. The red is
positive and the black is negative.