ZYNQ Ultr FPGA Board AXU5EV-P User Manual
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section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure
2-4-1 shows the QSPI Flash in the schematic.
Figure 2-4-1: QSPI Flash in the schematic
Configure chip pin assignments:
Signal Name
Pin Name
Pin Number
MIO0_QSPI0_SCLK
PS_MIO0_500
AG15
MIO1_QSPI0_IO1
PS_MIO1_500
AG16
MIO2_QSPI0_IO2
PS_MIO2_500
AF15
MIO3_QSPI0_IO3
PS_MIO3_500
AH15
MIO4_QSPI0_IO0
PS_MIO4_500
AH16
MIO5_QSPI0_SS_B
PS_MIO5_500
AD16
Part 2.5: eMMC Flash
The ACU5EV core board is equipped with a large-capacity 8GB eMMC
FLASH chip, the model is MTFC8GAKAJCN-4M, it supports the HS-MMC
interface of the JEDEC e-MMC V5.0 standard, and the level supports 1.8V or
3.3V. The data width of eMMC FLASH and ZYNQ connection is 8bit. Due to the
large-capacity and non-volatile characteristics of eMMC FLASH, it can be used
as a large-capacity storage device in the ZYNQ system, such as storing ARM
applications, system files and other user data files The specific models and
related parameters of eMMC FLASH are shown in Table 2-5-1.