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Alinx ZYNQ UltraScale+ User Manual Download Page 21

ZYNQ Ultr FPGA Board AXU5EV-P User Manual

21 / 66

www.alinx.com

PS_DDR4_CKE0

PS_DDR_CKE0_504

V28

PL Side DDR4 SDRAM pin assignment:

Signal Name

Pin Name

Pin Number

PL_DDR4_DQS0_P

IO_L22P_T3U_N6_DBC_AD0P_64

AE2

PL_DDR4_DQS0_N

IO_L22N_T3U_N7_DBC_AD0N_64

AF2

PL_DDR4_DQS1_P

IO_L16P_T2U_N6_QBC_AD3P_64

AD2

PL_DDR4_DQS1_N

IO_L16N_T2U_N7_QBC_AD3N_64

AD1

PL_DDR4_DQ0

IO_L24N_T3U_N11_64

AG1

PL_DDR4_DQ1

IO_L24P_T3U_N10_64

AF1

PL_DDR4_DQ2

IO_L23N_T3U_N9_64

AH1

PL_DDR4_DQ3

IO_L23P_T3U_N8_64

AH2

PL_DDR4_DQ4

IO_L21N_T3L_N5_AD8N_64

AF3

PL_DDR4_DQ5

IO_L21P_T3L_N4_AD8P_64

AE3

PL_DDR4_DQ6

IO_L20N_T3L_N3_AD1N_64

AH3

PL_DDR4_DQ7

IO_L20P_T3L_N2_AD1P_64

AG3

PL_DDR4_DQ8

IO_L18N_T2U_N11_AD2N_64

AC1

PL_DDR4_DQ9

IO_L18P_T2U_N10_AD2P_64

AB1

PL_DDR4_DQ10

IO_L17N_T2U_N9_AD10N_64

AC2

PL_DDR4_DQ11

IO_L17P_T2U_N8_AD10P_64

AB2

PL_DDR4_DQ12

IO_L15N_T2L_N5_AD11N_64

AB3

PL_DDR4_DQ13

IO_L15P_T2L_N4_AD11P_64

AB4

PL_DDR4_DQ14

IO_L14N_T2L_N3_GC_64

AC3

PL_DDR4_DQ15

IO_L14P_T2L_N2_GC_64

AC4

PL_DDR4_DM0

IO_L19P_T3L_N0_DBC_AD9P_64

AG4

PL_DDR4_DM1

IO_L13P_T2L_N0_GC_QBC_64

AD5

PL_DDR4_A0

IO_L8N_T1L_N3_AD5N_64

AG8

PL_DDR4_A1

IO_L3P_T0L_N4_AD15P_64

AB8

PL_DDR4_A2

IO_L8P_T1L_N2_AD5P_64

AF8

PL_DDR4_A3

IO_L3N_T0L_N5_AD15N_64

AC8

PL_DDR4_A4

IO_L11P_T1U_N8_GC_64

AF7

PL_DDR4_A5

IO_L4P_T0U_N6_DBC_AD7P_64

AD7

PL_DDR4_A6

IO_L9N_T1L_N5_AD12N_64

AH7

PL_DDR4_A7

IO_L2P_T0L_N2_64

AE9

Summary of Contents for ZYNQ UltraScale+

Page 1: ...ZYNQ UltraScale FPGA Development Board AXU5EV P User Manual...

Page 2: ...ZYNQ Ultrascale FPGA Board AXU5EV P User Manual 2 66 www alinx com Version Record Version Date Release By Description Rev 1 0 2021 06 17 Rachel Zhou First Release...

Page 3: ...8 Power Supply 28 Part 2 9 ACU5EV Core Board Size Dimension 29 Part 2 10 Board to Board Connectors pin assignment 29 Part 3 Carrier Board 38 Part 3 1 Carrier Board Introduction 38 Part 3 2 M 2 Interfa...

Page 4: ...t 3 15 FMC Interface 56 Part 3 16 JTAG Debug Port 59 Part 3 17 Real time Clock 60 Part 3 18 EEPROM and Temperature Sensor 60 Part 3 19 User LEDs 61 Part 3 20 Keys 62 Part 3 21 DIP Switch Configuration...

Page 5: ...1GB DDR4 SDRAM chip In the design of carrier board we have extended a wealth of interfaces for users such as 1 FMC LPC interface 1 SATA M 2 interface 1 DP interface 1 PCIe x 2 Interfaces 2 SPF Interfa...

Page 6: ...ZYNQ Ultrascale FPGA Board AXU5EV P User Manual 6 66 www alinx com...

Page 7: ...PS side and PL side of the ZU5EV chip there are 4 DDR4 and 1 DDR4 respectively each with a capacity of up to 1GB which enables the ARM system and FPGA system to independently process and store data T...

Page 8: ...DR4 PS 1GB DDR4 PL 8GB eMMC FLASH 256Mb QSPI FLASH and there are 2 crystal oscillators to provide the clock a single ended 33 3333MHz crystal oscillator for the PS system and a differential 200MHz cry...

Page 9: ...t chip adopts the USB UAR chip of Silicon Labs CP2102GM and the USB interface adopts the MINI USB interface PCIe x 2 Interface It supports the PCI Express 3 0 standard compatible with 2 0 provides a s...

Page 10: ...o way CAN bus interface using TI s SN65HVD232 chip the interface uses 4Pin green terminal blocks 485 Communication Interface Two way 485 communication interface using MAX3485 chip of MAXIM company The...

Page 11: ...k LED Lights 5 LEDs include 2 LEDs on the core board 3 LED on the carrier board There are 1 power indicator and 1 DONE Configuration indicator on the core board 1 power indicator on the carrier board...

Page 12: ...MHz data rate 2400Mbps and the highest operating speed of DDR4 SDRAM on the PL side can reach 1066MHz data rate 2132Mbps In addition a 256MBit QSPI FLASH and an 8GB eMMC FLASH chip are also integrated...

Page 13: ...up to 1 2Ghz and supports Level 2 Cache it also contains 2 Cortex R5 processors with a speed of up to 500Mhz The ZU5EV chip supports 32 bit or 64 bit DDR4 LPDDR4 DDR3 DDR3L LPDDR3 memory chips with r...

Page 14: ...nstruction and data cache 1MB level 2 cache shared by 2 CPUs ARM dual core Cortex R5 processor speed up to 600MHz each CPU 32KB level 1 instruction and data cache and 128K tightly coupled memory Image...

Page 15: ...he main parameters of the PL logic part are as follows System Logic Cells 256 2K CLB Flip flops 234 24K Look up tables LUTs 117 12K Block RAM 5 1 Mb Clock Management Units CMTs 4 DSP Slices 1248 Video...

Page 16: ...rface of the FPGA The specific configuration of DDR4 SDRAM is shown in Table 2 3 1 below Bit Number Chip Model Capacity Factory U12 U14 U15 U16 MT40A512M16LY 062E 512M x 16bit Micron Table 2 3 1 DDR4...

Page 17: ...21 PS_DDR4_DQS0_N PS_DDR_DQS_N0_504 AG21 PS_DDR4_DQS1_P PS_DDR_DQS_P1_504 AF23 PS_DDR4_DQS1_N PS_DDR_DQS_N1_504 AG23 PS_DDR4_DQS2_P PS_DDR_DQS_P2_504 AF25 PS_DDR4_DQS2_N PS_DDR_DQS_N2_504 AF26 PS_DDR4...

Page 18: ...Q11 PS_DDR_DQ11_504 AD22 PS_DDR4_DQ12 PS_DDR_DQ12_504 AH23 PS_DDR4_DQ13 PS_DDR_DQ13_504 AH24 PS_DDR4_DQ14 PS_DDR_DQ14_504 AE24 PS_DDR4_DQ15 PS_DDR_DQ15_504 AG24 PS_DDR4_DQ16 PS_DDR_DQ16_504 AC26 PS_DD...

Page 19: ...22 PS_DDR4_DQ45 PS_DDR_DQ45_504 H22 PS_DDR4_DQ46 PS_DDR_DQ46_504 K22 PS_DDR4_DQ47 PS_DDR_DQ47_504 L22 PS_DDR4_DQ48 PS_DDR_DQ48_504 M25 PS_DDR4_DQ49 PS_DDR_DQ49_504 M26 PS_DDR4_DQ50 PS_DDR_DQ50_504 L25...

Page 20: ...7_504 AA23 PS_DDR4_A8 PS_DDR_A8_504 AA22 PS_DDR4_A9 PS_DDR_A9_504 AB23 PS_DDR4_A10 PS_DDR_A10_504 AA25 PS_DDR4_A11 PS_DDR_A11_504 AA26 PS_DDR4_A12 PS_DDR_A12_504 AB25 PS_DDR4_A13 PS_DDR_A13_504 AB26 P...

Page 21: ...4_DQ6 IO_L20N_T3L_N3_AD1N_64 AH3 PL_DDR4_DQ7 IO_L20P_T3L_N2_AD1P_64 AG3 PL_DDR4_DQ8 IO_L18N_T2U_N11_AD2N_64 AC1 PL_DDR4_DQ9 IO_L18P_T2U_N10_AD2P_64 AB1 PL_DDR4_DQ10 IO_L17N_T2U_N9_AD10N_64 AC2 PL_DDR4...

Page 22: ..._DDR4_CLK_N IO_L10N_T1U_N7_QBC_AD4N_64 AG5 PL_DDR4_CLK_P IO_L10P_T1U_N6_QBC_AD4P_64 AG6 PL_DDR4_CKE IO_T3U_N12_64 AE4 PL_DDR4_OTD IO_L19N_T3L_N1_DBC_AD9N_64 AH4 Part 2 4 QSPI Flash The FPGA core board...

Page 23: ...0_IO3 PS_MIO3_500 AH15 MIO4_QSPI0_IO0 PS_MIO4_500 AH16 MIO5_QSPI0_SS_B PS_MIO5_500 AD16 Part 2 5 eMMC Flash The ACU5EV core board is equipped with a large capacity 8GB eMMC FLASH chip the model is MTF...

Page 24: ...the system design it is necessary to configure the GPIO port function of the PS side as an EMMC interface Figure 2 5 1 shows the part of eMMC Flash in the schematic diagram Figure 2 5 1 QSPI Flash in...

Page 25: ...ependently The schematic diagram of the clock circuit design is shown in Figure 2 6 1 Figure 2 6 1 Core Board Clock Source PS System RTC Real Time Clock The passive crystal Y2 on the core board provid...

Page 26: ...hip The schematic diagram is shown in Figure 2 6 3 Figure 2 6 3 Active Crystal in PS part Clock pin assignment Signal Name Pin PS_CLK R16 PL System Clock Source The core board provides a differential...

Page 27: ..._N AF5 Part 2 7 LED There is a red power indicator PWR and a configuration LED DONE on the ACU5EV core board When the core board is powered on the power indicator will light up after the FPGA configur...

Page 28: ...is DC12V which is supplied by connecting the carrier board The core board uses a PMIC chip TPS6508641 to generate all the power required by the XCZU5EV chip For the TPS6508641 power supply design ple...

Page 29: ...re board has a total of four high speed expansion ports It uses four 120 pin inter board connectors J29 J30 J31 J32 to connect to the carrier board The connectors used is Panasonic AXK5A2137YG and the...

Page 30: ...B65_L2_P U9 4 B65_L22_N K7 5 GND 6 GND 7 B65_L4_N T8 8 B65_L20_P J6 9 B65_L4_P R8 10 B65_L20_N H6 11 GND 12 GND 13 B65_L1_N Y8 14 B65_L6_N T6 15 B65_L1_P W8 16 B65_L6_P R6 17 GND 18 GND 19 B65_L7_P L1...

Page 31: ...ND 78 GND 79 B66_L16_P G8 80 B65_L23_P K9 81 B66_L16_N F7 82 B65_L23_N J9 83 GND 84 GND 85 B66_L15_P G6 86 B66_L5_N E3 87 B66_L15_N F6 88 B66_L5_P E4 89 GND 90 GND 91 B66_L4_P G3 92 B66_L2_P E1 93 B66...

Page 32: ...21 B66_L24_N B9 22 B66_L17_N E8 23 GND 24 GND 25 B66_L23_N A8 26 B25_L9_P C11 27 B66_L23_P A9 28 B25_L9_N B10 29 GND 30 GND 31 B25_L5_N F10 32 B25_L10_P B11 33 B25_L5_P G11 34 B25_L10_N A10 35 GND 36...

Page 33: ...2 95 GND 96 GND 97 505_TX3_P B23 98 505_TX1_P D23 99 505_TX3_N B24 100 505_TX1_N D24 101 GND 102 GND 103 505_RX3_P A25 104 505_TX0_P E25 105 505_RX3_N A26 106 505_TX0_N E26 107 GND 108 GND 109 505_TX2...

Page 34: ...B9 38 B44_L9_P AA11 39 B44_L12_P AB10 40 B44_L9_N AA10 41 GND 42 GND 43 B44_L10_N Y10 44 B44_L3_P AH12 45 B44_L10_P W10 46 B44_L3_N AH11 47 GND 48 GND 49 B24_L11_N W11 50 B44_L1_N AH10 51 B24_L11_P W1...

Page 35: ...224_RX1_N V1 112 224_TX1_N U3 113 GND 114 GND 115 224_RX0_P Y2 116 224_TX0_P W4 117 224_RX0_N Y1 118 224_TX0_N W3 119 GND 120 GND Pin assignment of board to board connector J32 J32 Pin Signal Name Pi...

Page 36: ...S_MIO44 J20 56 PS_MIO67 B18 57 PS_MIO45 K20 58 PS_MIO68 C18 59 GND 60 GND 61 PS_MIO47 H21 62 PS_MIO64 E19 63 PS_MIO48 J21 64 PS_MIO69 D19 65 GND 66 GND 67 PS_MIO41 J19 68 PS_MIO74 D20 69 PS_MIO32 J16...

Page 37: ...oard AXU5EV P User Manual 37 66 www alinx com 101 VCCO_65 102 VCCO_66 103 VCCO_65 104 VCCO_66 105 GND 106 GND 107 12V 108 12V 109 12V 110 12V 111 12V 112 12V 113 12V 114 12V 115 12V 116 12V 117 12V 11...

Page 38: ...camera interface 1 Channel HDMI video output interface 1 Channel HDMI video input interface 1 Channel FMC interface 2 Channel CAN communication interfaces 2 Channel 485 communication interfaces JTAG...

Page 39: ...M 2 Interface Schematic The pin assignment of M 2 interface ZYNQ is as follows Signal Name Pin Name Pin Number Description PCIE_TX_P 505_TX0_P E25 PCIE Data Transmit Positive PCIE _TX_N 505_TX0_N E26...

Page 40: ...ector in a differential signal mode The DisplayPort auxiliary channel is connected to the MIO pin of the PS The schematic diagram of the DP output interface design is shown in Figure 3 3 1 Figure 3 3...

Page 41: ...re are 4 USB3 0 ports on the AXU5EV P carrier board supporting the HOST working mode and the data transmission speed is up to 5 0Gb s USB3 0 is connected through the PIPE3 interface and USB2 0 is conn...

Page 42: ...D16 USB2 0 Data Direction Signal USB_CLK PS_MIO52 G18 USB2 0 Clock Signal USB_NXT PS_MIO55 B16 USB2 0 Next Data Signal USB_RESET_N PS_MIO31 H16 USB2 0 Reset Signal Part 3 5 Gigabit Ethernet Interface...

Page 43: ...plex Table 3 5 1 PHY chip default configuration value When the network is connected to Gigabit Ethernet the data transmission of ZYNQ and PHY chip KSZ9031RNX is communicated through the RGMII bus the...

Page 44: ..._MIO74 D20 Ethernet 1 Receive Data Bit3 PHY1_RXCTL PS_MIO75 A19 Ethernet 1 Receive Enable Signal PHY1_MDC PS_MIO76 B20 Ethernet 1 MDIO Clock Management PHY1_MDIO PS_MIO77 F20 Ethernet 1 MDIO Managemen...

Page 45: ...t for serial data communication The schematic diagram of the USB Uart circuit design is shown in the figure below The schematic diagram of the USB Uart circuit design is shown in Figure 3 6 1 Figure 3...

Page 46: ...the PS BANK501 of ZU4EV Since the VCCMIO of the BANK is set to 1 8V but the data level of the SD card is 3 3V connected through the TXS02612 level shifter The schematic of the Zynq7000 PS and SD card...

Page 47: ...U4EV PL part The ZYNQ UltraScale system initializes and controls the ADV7511 through the I2C pin The hardware connection diagram of ADV7511 chip and ZYNQ UltraScale is shown in Figure 3 8 1 Figure 3 8...

Page 48: ...HDMI_D15 B35_L18_P B17 HDMI Video Signal Data15 HDMI_D16 B35_L15_N E17 HDMI Video Signal Data16 HDMI_D17 B35_L15_P F17 HDMI Video Signal Data17 HDMI_D18 B35_L7_N G16 HDMI Video Signal Data18 HDMI_D19...

Page 49: ...IN_HS B44_L12_N AA12 HDMI Input Video Signal Column Synchronization HDMI_IN_VS B44_L12_P Y12 HDMI Input Video Signal Enable HDMI_IN_DE B44_L7_P AA13 HDMI Input Video Signal Data0 HDMI_IN_D0 B44_L10_P...

Page 50: ...W14 HDMI Input Video Signal Data20 HDMI_IN_D20 B44_L8_P AB15 HDMI Input Video Signal Data21 HDMI_IN_D21 B44_L8_N AB14 HDMI Input Video Signal Data22 HDMI_IN_D22 B43_L2_N AG11 HDMI Input Video Signal D...

Page 51: ...ve Negative SFP1_RX_P 224_RX0_P Y2 Optical Module 1 Data Receive Positive SFP2_TX_N 224_TX1_N U3 Optical Module 2 Data Transmit Negative SFP2_TX_P 224_TX1_P U4 Optical Module 2 Data Transmit Positive...

Page 52: ...face is directly connected to the GTH transceiver of ZYNQ BANK224 and the single channel communication rate can be as high as 8G bit bandwidth The PCIe interface schematic is shown in Figure 3 11 belo...

Page 53: ...3_L8_N AC11 PCIE Board Reset Signal Part 3 12 CAN Communication Interface There are 2 CAN communication interfaces on the AXU5EV P carrier board which are connected to the MIO interface of the BANK501...

Page 54: ...or the user s 485 communication service Figure 3 13 1 is the connection diagram of the 485 transceiver chip on the PL side Figure 3 13 1 485 Communication on the PL Side The 485 communication pins are...

Page 55: ...BANK65 the level standard is 1 2V The jumper of J43 needs to be connected to PIN2 and PIN3 pins other control signals are connected to the IO of BANK43 level standard It is 3 3V The circuit schematic...

Page 56: ...e The AXU5EV P FPGA Carrier board has a standard FMC HPC expansion port that can be connected to various FMC modules of XILINX or ALINX HDMI input and output modules binocular camera modules high spee...

Page 57: ..._LA03_P B65_L4_P R8 FMC Reference 3rd Data P FMC_LA03_N B65_L4_N T8 FMC Reference 3rd Data N FMC_LA04_P B65_L7_P L1 FMC Reference 4th Data P FMC_LA04_N B65_L7_N K1 FMC Reference 4th Data N FMC_LA05_P...

Page 58: ...Data N FMC_LA20_P B66_L2_P E1 FMC Reference 20th Data P FMC_LA20_N B66_L2_N D1 FMC Reference 20th Data N FMC_LA21_P B66_L15_P G6 FMC Reference 21st Data P FMC_LA21_N B66_L15_N F6 FMC Reference 21st Da...

Page 59: ...6_L8_N A1 FMC Reference 33rd Data N FMC_PRSNT B45_L12_N C12 FMC Module Exist Signal PWRGD B44_L2_N AH14 FMC Power Good Signal Part 3 16 JTAG Debug Port The JTAG interface is reserved on the AXU5EV P e...

Page 60: ...f it is generally necessary to equip the coin battery model LR1130 voltage is 5V to supply power to the clock chip The BT1 on the development board is a battery Socket After we put the coin battery ev...

Page 61: ...Q Pin Name ZYNQ Pin Number Description PS_IIC1_SCL PS_MIO24 AB19 I2C Clock Signal PS_IIC1_SDA PS_MIO25 AB21 I2C Data Signal Part 3 19 User LEDs There are 3 LEDs on the AXU5EV P Carrier board including...

Page 62: ...AE15 User LED controlled by PL Part 3 20 Keys There are 1 reset KEY RESET and 2 user buttons on the AXU5EV P carrier board The reset signal is connected to the reset chip input of the core board ACU4...

Page 63: ...it DIP switch SW1 on the FPGA development board to configure the startup mode of the ZYNQ system The AXU5EV P system development platform supports 4 startup modes The 4 startup modes are JTAG debug mo...

Page 64: ...is converted into 5V 3 3V and 1 8V through one way DC DC power chip TPS54620 and two way DC DC power chip MP1482 In addition the Carrier board generates 1 2V through LDO to supply power to the core b...

Page 65: ...heat sink and fan to the chip on the board to prevent the chip from overheating The control of the fan is controlled by the ZYNQ chip The control pin is connected to the IO of the BANK44 AG14 If the...

Page 66: ...ZYNQ Ultrascale FPGA Board AXU5EV P User Manual 66 66 www alinx com Part 3 24 Carrier Board Size Dimension Figure 3 24 1 Top View...

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