ZYNQ Ultr FPGA Board AXU5EV-P User Manual
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86
-
-
86
-
-
87
-
-
88
-
-
89
GND
-
90
GND
-
91
224_CLK0_P
Y6
92
224_CLK1_P
V6
93
224_CLK0_N
Y5
94
224_CLK1_N
V5
95
GND
-
96
GND
-
97
224_RX3_P
P2
98
224_TX3_P
N4
99
224_RX3_N
P1
100
224_TX3_N
N3
101
GND
-
102
GND
-
103
224_RX2_P
T2
104
224_TX2_P
R4
105
224_RX2_N
T1
106
224_TX2_N
R3
107
GND
-
108
GND
-
109
224_RX1_P
V2
110
224_TX1_P
U4
111
224_RX1_N
V1
112
224_TX1_N
U3
113
GND
-
114
GND
-
115
224_RX0_P
Y2
116
224_TX0_P
W4
117
224_RX0_N
Y1
118
224_TX0_N
W3
119
GND
-
120
GND
-
Pin assignment of board to board connector J32
J32 Pin
Signal Name
Pin Number
J32 Pin
Signal Name
Pin Number
1
PS_MIO35
H17
2
PS_MIO30
F16
3
PS_MIO29
G16
4
PS_MIO31
H16
5
GND
-
-
GND
-
7
-
-
8
PS_MIO58
F18
9
-
-
10
PS_MIO53
D16
11
GND
-
12
GND
-
13
PS_MODE0
P19
14
PS_MIO52
G18
15
PS_MODE1
P20
16
PS_MIO55
B16
17
GND
-
18
GND
-
19
PS_MODE2
R20
20
PS_MIO56
C16
21
PS_MODE3
T20
22
PS_MIO57
A16
23
GND
-
24
GND
-
25
PS_MIO36
K17
26
PS_MIO54
F17
27
PS_MIO37
J17
28
PS_MIO27
J15