KX400+ series mainboard
45
Advanced Chipset Features
DRAM Clock/Drive Control
Press <Enter> to enter next page for DRAM Clock/Drive Control settings.
DRAM CAS Latency
This item determines DRAM CAS Latency. When synchronous DRAM is installed,
the number of clock cycles of CAS latency depends on the DRAM timing. Do not
reset this field from the default value specified by the system designer. Options: 2.5
(default)
、
2
DRAM Timing
This item determines DRAM clock/ timing by SPD or manual configuration.
Options: By SPD (default)
、
Manual
Precharge to Active (Trp)
You can set the time to precharge. Options: 3T (default)
、
2T
Active to Precharge (Tras)
Set the DRAM type to select the number of DRAM timing. Options: 6T (default)
、
5T
Active to CMD (Trcd)
Select the DRAM delay time when being read. Options: 3T (default)
、
2T
DRAM Burst Length
This item determines DRAM Burst Length. Options: 4 (default)
、
8.
DRAM Queue Depth
This item determines DRAM Queue Depth. Options: 2 level
、
3 level
、
4 level (default).
DRAM Command Rate
The item determines DRAM Command Rate.
Options: 2T Command(default)
、
1T Command.
AGP & P2P Bridge Control
If you highlight the literal “Press Enter” next to the “AGP & P2P Bridge Control” label
and then press the enter key, it will take you a submenu with the following options:
