ASAHI KASEI
[AKD4633-A]
<KM079407>
2016/10
- 4 -
(2) Evaluation of loop-back mode (A/D
D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
a) Set up jumper pins of MCKI clock
X’tal of 12.288MHz (Default) is set on the AKD4633-A. In this case, the AK4633VN corresponds to PLL
reference clock of 12.288MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4633VN is
supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then “MCKO bit”
in the AK4633VN should be set to “1”. When an external clock through a RCA connector (J8: EXT/BICK) is
supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly
selected in order to match the output impedance of the clock generator.
b) Set up jumper pins of BICK clock
c) Set up jumper pins of FCK clock
d) Set up jumper pins of DATA
When the AK4633VN is evaluated by loop-back mode (A/D
D/A), the jumper pins should be set to the
following.
JP17
XTE
MCLK_SEL
JP21
JP18
MKFS
256fs 512fs 1024fs
XTL DIR
EXT
MCKO
JP6
MCKI
JP28
FCK
ADC
DIR
JP22
FCK_SEL
2fs
EXT
1fs
JP26
4631_SDTI
ADC
DAC/LOOP
JP30
SDTI
DIR
ADC
JP29
JP20
BICK
JP27
BICK_INV
THR
INV
DIR ADC
BICK
THR
INV
BICK_SEL
JP19
EXT
16fs
32fs
64fs
