AKM AK4534, Manual

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ASAHI KASEI [AK4537]
MS0202-E-04 2005/04
- 69 -
„ Stop of Clock
MCLK can be stopped when PMMIC=PMADC=PMDAC=PMSPK= “0”.
1. When X’tal is used in PLL mode
MCKPD bit
(Addr:01H, D7)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:03H, D4)
(1)
(2)
E x a m p le :
A u d io I/F F o rm a t : I
2
S
B IC K fre q u e n c y a t M a s te r M o d e : 6 4 fs
In p u t M a s te r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O u tp u t M a s te r C lo c k F re q u e n c y : 6 4 fs
(1 ) A d d r:0 4 H , D a ta :6 2 H
(2 ) A d d r:0 1 H , D a ta :8 0 H
Figure 57. Stop of Clock Sequence(1)
<Example>
(1) Disable MCKO output : MCKO bit = “1”
o
“0”
(2) Power down X’tal and PLL, Pull down the XTI pin :
PMXTL bit = PMPLL bit = “1”
o
“0”, MCKPD = “0”
o
“1”
2. When an external clock is used in PLL mode
MCKPD bit
(Addr:01H, D7)
External MCLK
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:03H, D4)
Input
(1)
(2)
(3)
E x a m p le :
A u d io I/F : I
2
S
B IC K fre q u e n c y a t M a s te r M o d e : 6 4 fs
In p u t M a s te r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O u tp u t M a s te r C lo c k F re q u e n c y : 6 4 fs
(1 ) A d d r:0 4 H , D a ta :6 2 H
(2 ) A d d r:0 1 H , D a ta :8 0 H
(3 ) S to p e x te rn a l c lo c k
Figure 58. Stop of Clock Sequence(2)
<Example>
(1) Stop MCKO output : MCKO bit = “1”
o
“0”
(2) Power down PLL, Pull down the XTI pin : PMPLL bit = “1”
o
“0”, MCKPD = “0”
o
“1”
When the external MCLK becomes Hi-Z or the external MCLK is input by AC couple, MCKI pin should be
pulled down.
(3) Stop an external MCLK
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