AKM AK4534, Manual

Page: 56 / 76

ASAHI KASEI [AK4537]
MS0202-E-04 2005/04
- 56 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0BH Lch Input PGA Control 0 IPGAL6 IPGAL5 IPGAL4 IPGAL3 IPGAL2 IPGAL1 IPGAL0
0FH Rch Input PGA Control 0 IPGAR6 IPGAR5 IPGAR4 IPGAR3 IPGAR2 IPGAR1 IPGAR0
R/W RD R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 1 0 0 0 0
IPGAL6-0: Lch Input Analog PGA (see Table 32)
IPGAR6-0: Rch Input Analog PGA (see Table 32)
Default: “10H” (0dB)
When IPGA gain is changed, IPGAL6-0 and IPGAR6-0 bits should be written while PMMICL, PMMICR,
PMIPGL or PMIPGR bit is “1” and ALC1 bit is “0”. IPGA gain is reset when PMMICL=PMMICR=PMIPGL
=PMIPGR= “0”, and then IPGA operation starts from the default value when PMMICL, PMMICR, PMIPGL
or PMIPGR bit is changed to “1”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value
set by ALC1 operation. When IPGAL6-0 and IPGAR6-0 bits are read, the register values written by the last
write operation are read out regardless the actual gain.
GAIN (dB)
DATA (HEX)
MIC Input LINE Input
STEP
47 +27.5 +12.0
46 +27.0 +11.5
45 +26.5 +11.0
: : :
36 +19.0 +3.5
: : :
2F +15.5 +0.0
: : :
10 +0.0 -15.5 Default
: : :
06
5.0 20.5
05
5.5 21.0
04 6.0 21.5
03 6.5 22.0
02 7.0 22.5
01 7.5 23.0
00
8.0 23.5
0.5dB
Table 32. Input Gain Setting
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0CH Lch Digital ATT Control ATTL7 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0
0DH Rch Digital ATT Control ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
ATTL/R7-0: Digital ATT Output Control (see Table 18)
Default: “00H” (0dB)
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