AKM AK4534 Manual Download Page 53

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ASAHI KASEI

[AK4537]

MS0202-E-04

2005/04

Addr

Name

D7 D6 D5 D4 D3 D2 D1 D0

08H

Timer

Select

ROTM ZTM1 ZTM0 WTM1

WTM0 LTM1 LTM0

R/W

RD R/W R/W R/W R/W R/W R/W R/W

Default

0 0 0 0 0 0 0 0

LTM1-0: ALC1

limiter

operation period at zero crossing disable (ZELM bit = “1”) (see Table 25)

The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done
by the period specified by the LTM1-0 bits. Default is “00” (0.5/fs).

ALC1 Limiter Operation Period

LTM1 LTM0

8kHz

16kHz

44.1kHz

0 0

0.5/fs

s 31

s 11

Default

0 1 1/fs

125

s 63

s 23

1 0 2/fs

250

s 125

s 45

1 1 4/fs

500

s 250

s 91

Table 25. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit = “1”)

WTM1-0: ALC1 Recovery Waiting Period (see Table 26)

A period of recovery operation when any limiter operation does not occur during the ALC1 operation.
Default is “00” (128/fs).

ALC1 Recovery Operation Waiting Period

WTM1 WTM0

8kHz

16kHz

44.1kHz

0 0

128/fs

16ms 8ms 2.9ms

Default

0 1

256/fs

32ms 16ms 5.8ms

1 0

512/fs

64ms 32ms

11.6ms

1 1

1024/fs

128ms 64ms

23.2ms

Table 26. ALC1 Recovery Operation Waiting Period

ZTM1-0: Zero crossing timeout for the write operation by the

P, ALC1 recovery, and zero crossing enable (ZELM

bit = “0”) of the ALC1 operation. (see Table 27)

When the IPGA of each L/R channels perform zero crossing or timeout independently, the IPGA value is
changed by the

P WRITE operation, ALC1 recovery operation or ALC1 limiter operation (ZELM bit = “0”).

Default is “00” (128/fs).

Zero Crossing Timeout Period

ZTM1 ZTM0

8kHz

16kHz

44.1kHz

0 0

128/fs

16ms 8ms 2.9ms

Default

0 1

256/fs

32ms 16ms 5.8ms

1 0

512/fs

64ms 32ms

11.6ms

1 1

1024/fs

128ms 64ms

23.2ms

Table 27. Zero Crossing Timeout Period

ROTM:

Period time for ALC2 Recovery operation

0: 2048/fs (Default)
1: 512/fs

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Summary of Contents for AK4534

Page 1: ...32kHz 44 1kHz 48kHz x Digital Volume 0dB a 127dB 0 5dB Step Mute x Stereo Headphone Amp S N D 70dB S N 90dB Output Power 15mW 16 HVDD 3 3V Click Noise Free at Power ON OFF x Mono Speaker Amp with ALC...

Page 2: ...PL xxx xxx xxx xxx xxx xxx xxx xxx PMHPL HP AMP HPR xxx xxx xxx xxx xxx xxx xxx PMHPR HP AMP Control Register Interface Audio PMSPK SPK AMP SPP SPN I2C CSN CAD1 CCLK SCL CDTI SDA CDTO PMMO CAD0 MOUT X...

Page 3: ...9 24 23 22 21 20 19 18 17 16 15 14 2 3 4 5 6 7 8 9 10 11 AK4537VN Top View MPE MPI INT MICL VCOM AVSS AVDD PVDD PVSS CCLK SCL DVDD DVSS XTO XTI MCKI M S SPP SPN HVDD HVSS HPR HPL BEEPL BEEPR BEEPM LIN...

Page 4: ...added 01H SPKG SPK Amp Output Power Select is added 02H MOGN MOUT Gain Select is added MICM IPGA Lch o MOUT is added 03H PSLO Stereo Line Output Power Save Mode Select is added MICL IPGA Lch o LOUT R...

Page 5: ...O Output Pin for Loop Filter of PLL Circuit This pin should be connected to PVSS with one resistor and capacitor in series 13 NC No Connect This pin should be left floating 14 CAD0 I Chip Address 0 S...

Page 6: ...ant Control Pin Connected to HVSS pin with a capacitor for mute time constant 40 MIN I ALC Input Pin 41 MOUT2 O Analog Mixing Output Pin 42 ROUT O Rch Stereo Line Output Pin 43 LOUT O Lch Stereo Line...

Page 7: ...and HVSS must be connected to the same analog ground plane WARNING Operation at or beyond these limits may result in permanent damage to the device Normal operation is not guaranteed at these extremes...

Page 8: ...60dBFS A weighted Note 8 91 dB Note 7 75 83 dB S N A weighted Note 8 91 dB Note 7 75 90 dB Interchannel Isolation Note 8 100 dB Note 7 0 1 0 5 dB Interchannel Gain Mismatch Note 8 0 1 0 5 dB DAC Char...

Page 9: ...C2 in Figure 2 300 pF Speaker Amp Characteristics RL 8 BTL DAC o MOUT2 o MIN o SPP SPN ALC2 OFF Output Voltage SPKG 0 Po 150mW 2 47 3 09 3 71 Vpp Note 12 SPKG 1 Po 300mW 4 38 Vpp SPKG 0 Po 150mW 50 64...

Page 10: ...Vin 0 6 x AVDD Note 15 When ALC2 Gain is changed this typical value changes between 22k and 26k Note 16 Output Voltage is proportional to AVDD voltage Vout 0 588 x AVDD Note 17 When the output pin dri...

Page 11: ...0 0kHz FR r0 5 dB BOOST Filter Note 24 MIN 20Hz FR 5 74 dB 100Hz 2 92 dB 1kHz 0 0 dB MID 20Hz FR 5 94 dB 100Hz 4 71 dB 1kHz 0 14 dB MAX 20Hz FR 16 04 dB 100Hz 10 55 dB Frequency Response 1kHz 0 3 dB N...

Page 12: ...LK ns MCKO Output Frequency fMCK 0 256 12 288 MHz Duty Cycle except fs 32kHz dMCK 40 50 60 fs 32kHz at 256fs Note 27 dMCK 33 LRCK Timing Frequency fs 8 48 kHz Duty Cycle Slave mode Duty 45 55 Master m...

Page 13: ...s Clock Low Time tLOW 4 7 Ps Clock High Time tHIGH 4 0 Ps Setup Time for Repeated Start Condition tSU STA 4 7 Ps SDA Hold Time from SCL Falling Note 29 tHD DAT 0 Ps SDA Setup Time from SCL Rising tSU...

Page 14: ...LKL VIH VIL 1 fs LRCK VIH VIL tBCK BICK tBCKH tBCKL VIH VIL MCKO dMCK dMCK 50 DVDD fMCK Figure 3 Clock Timing MCKI Input Measurement Point AGND tACW tACW AGND 1 fCLK 1000pF 100k VAC Figure 4 MCKI AC C...

Page 15: ...RS SDTO 50 DVDD tLRB tBSD tSDS SDTI VIL tSDH VIH Figure 5 Audio Interface Timing Slave mode LRCK VIH VIL BICK 50 DVDD SDTO 50 DVDD tBSD tSDS SDTI VIL tSDH VIH tMBLR dBCK Figure 6 Audio Interface Timin...

Page 16: ...CDS VIH VIL CDTI VIH tCCKH tCCKL tCDH VIL C1 C0 R W CDTO Hi Z Figure 7 WRITE READ Command Input Timing CSN VIH VIL tCSH CCLK VIH VIL CDTI VIH tCSW VIL D1 D0 CDTO Hi Z D2 Figure 8 WRITE Data Input Timi...

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Page 19: ...an external clock is input directly to the XTI pin and indirect where the external clock is input through a capacitor Master Clock Status PMXTL bit MCKPD bit X tal Oscillator Figure 13 Oscillator ON...

Page 20: ...e 14 External Clock mode Input CMOS Level Note This clock level must not exceed DVDD level 3 AC Coupling Input XTI XTO AK4537 25k MCKPD 0 PMXTL 1 External Clock C Figure 15 External Clock mode Input t...

Page 21: ...tion PMPLL bit 1 the internal PLL continues to oscillate a few MHz and LRCK and BICK outputs go to L Table 5 In slave mode the LRCK input should be synchronized with MCKO The master clock MCKI should...

Page 22: ...PS1 0 bits are changed before LRCK is input MCKO is not output PS1 0 bits should be changed after LRCK is input in slave mode The master clock frequency should be changed only when the PMADL PMADR an...

Page 23: ...worse than at high sampling frequencies due to out of band noise When the out of band noise can be improved by using higher frequency of the master clock The S N of the DAC output through Headphone a...

Page 24: ...xxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxxxxxx xxx...

Page 25: ...17 Mode 1 Timing LRCK BICK 32fs SDTO o SDTI i 0 15 14 15 14 1 10 2 3 7 7 6 5 4 3 2 1 0 6 5 4 3 1 0 2 9 11 12 13 14 15 0 1 2 3 15 14 1 0 7 6 5 4 3 2 1 0 10 9 11 12 13 14 15 BICK 64fs 0 1 16 2 3 17 18...

Page 26: ...cases MICOUTL MICOUTR INT EXT MSEL 0 Internal MIC PMMICL bit 1 PMMICR bit 0 External MIC Figure 19 Internal MIC Mono MICOUTL MICOUTR INT EXT MSEL 1 External MIC PMMICL bit 1 PMMICR bit 0 Internal MIC...

Page 27: ...signal level equals or exceeds LMTH When the ZELM bit 0 the timeout period is set by the ZTM1 0 bits This enables the zero crossing attenuation function so that the IPGA value is attenuated at the ze...

Page 28: ...tep ALC1 ALC1 Enable bit 1 Enable 1 Enable 1 Enable Table 15 Example of the ALC1 setting The following registers should not be changed during the ALC1 operation These bits should be changed after the...

Page 29: ...oost applied to the DAC output signal Table 17 If the BST1 0 bits are set to 10 MID Level use a 47PF capacitor for AC coupling If the boosted signal exceeds full scale the analog output clips to the f...

Page 30: ...bits When the SMUTE bit is returned to 0 the mute is cancelled and the output attenuation gradually changes to 0dB during the cycle set of the TM1 0 bits If the soft mute is cancelled within the cycle...

Page 31: ...er output The external resisters Ri adjust the signal level of each BEEP input that are mixed to Headphone and Speaker outputs The signal from the BEEPM pin is mixed to the Headphone amp through a 20d...

Page 32: ...d HPR pins go to L HVSS PMHPL R bit HPL R bit HPL R pin 1 2 4 3 Figure 26 Power up Power down Timing for Headphone amp 1 Headphone amp power up HPL HPR bit 0 The outputs are still HVSS 2 Headphone amp...

Page 33: ...er than 12 put an oscillation prevention circuit 0 22PFr20 capacitor and 10 r20 resistor because it has the possibility that Headphone amp oscillates AK4537 HP AMP 16 Headphone 10 0 22P R xxxxx xxxxx...

Page 34: ...xxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxx...

Page 35: ...by current is increased Capacitor size affects the cut off frequency of 1st order LPF made by this AC coupling capacitor and series resister in front of BEEP input 2 Internal feedback resister of BEEP...

Page 36: ...TR7 0 bits set the volume control of DAC output ATTS3 0 bits set the volume control of IPGA Lch output Mono Output MOUT MOUT pins ATT DAC MIC In 0dB 20dB IPGA Lch MOUT 1 2 MOUT 17dB 6dB 1 2 MICM DAMO...

Page 37: ...the ALC2 limiter or recovery operations are not done When the PMSPK bit changes from 0 to 1 the initilization cycle 2048 fs 46 4ms fs 44 1kHz at ROTM bit 0 512 fs 11 4ms fs 44 1kHz at the ROTM bit 1...

Page 38: ...dBV 20dBV 30dBV 23 3dBV 8dB 15 3dBV 11 3dBV 3 3dBV FS 4 1dB 7 2dBV 8 1dB 16 1dB 4 1dB 1 9dB 8 2dB 8dB Single ended DATT DAC ALC2 SPK AMP 3 0dBV 250mW 8ohm 8 2dB 2 2dB 5 0dBV 2 2dB Figure 34 Speaker am...

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Page 40: ...transfer is always terminated by a STOP condition generated by the master A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition Figure 42 The AK4537 can perform more than...

Page 41: ...x xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xxxxxx xx...

Page 42: ...acknowledge DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER 1 9 8 START CONDITION not acknowledge clock pulse for acknowledgement S 2 Figure 43 Acknowledge on the I2 C Bus SCL SDA data line stable...

Page 43: ...mer Select 0 ROTM ZTM1 ZTM0 WTM1 WTM0 LTM1 LTM0 09H ALC Mode Control 1 0 ALC2 ALC1 ZELM LMAT1 LMAT0 RATT LMTH 0AH ALC Mode Control 2 0 REF6 REF5 REF4 REF3 REF2 REF1 REF0 0BH Lch Input PGA Control 0 IP...

Page 44: ...up PMIPGL IPGA Lch Block Power Control 0 Power down Default 1 Power up IPGA Lch Block is powered up if PMMICL or PMIPGL bit is 1 see Table 23 PMMICL PMIPGL MIC Amp IPGA 0 0 Power down Power down 0 1 P...

Page 45: ...thout these clocks Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Power Management 2 MCKPD PMXTL PMPLL SPKG PMSPK PMHPL PMHPR PMDAC R W R W R W R W R W R W R W R W R W Default 1 0 0 0 0 0 0 0 PMDAC DA...

Page 46: ...Mono BEEP signal BEEPM pin is mixed to Speaker amp at the BPMSP bit 1 BPSSP BEEPL BEEPR to Speaker amp Enable 0 OFF Default 1 ON Stereo BEEP signals BEEPL BEEPR pins are mixed to Speaker amp at the B...

Page 47: ...AHI KASEI AK4537 MS0202 E 04 2005 04 47 DAC DAHS BEEPM BEEPL BPMSP BEEPR BPSSP MIX MOUT2 ALC2 ALCS SPK Figure 45 Speaker amp switch control Downloaded from Elcodis com electronic components distributo...

Page 48: ...ault 1 ON Stereo BEEP signals BEEPL BEEPR is mixed to Headphone amp at the BPSHP bit 1 MICL IPGA Lch to Stereo Line Output Headphone amp and MOUT2 Enable 0 OFF Default 1 ON IPGA Lch signal is mixed to...

Page 49: ...Format Select see Table 13 Default 10 ADC I2 S DAC I2 S BF BICK frequency Select at Master Mode 0 64fs Default 1 32fs This bit is invalid in slave mode MCKO Master Clock Output Enable 0 Disable Defau...

Page 50: ...PMSPK bit 1 this bit is valid After the PDN pin changes from L to H the PMSPK bit is 0 which powers down Speaker amp LOOP Loopback ON OFF 0 OFF Default 1 ON When this bit is 1 the ADC output is passed...

Page 51: ...Mode Select 0 Independent 1 Dependent Default When DATTC 1 ATTL7 0 bits control both Lch and Rch at same time ATTR7 0 bits are not changed when the ATTL7 0 bits are written SMUTE Soft Mute Control 0 N...

Page 52: ...FF Default 1 ON ALC1 output signal is input to ADC when MICAD bit 1 MPWRI Power Supply Control for Internal Microphone 0 OFF Default 1 ON The setting of MPWRI is enabled when PMMICL bit 1 MPWRE Power...

Page 53: ...not occur during the ALC1 operation Default is 00 128 fs ALC1 Recovery Operation Waiting Period WTM1 WTM0 8kHz 16kHz 44 1kHz 0 0 128 fs 16ms 8ms 2 9ms Default 0 1 256 fs 32ms 16ms 5 8ms 1 0 512 fs 64...

Page 54: ...dB x 2 When the IPGA value exceeds the reference level REF6 0 bits the IPGA value does not increase RATT GAIN STEP 0 1 Default 1 2 Table 29 ALC1 Recovery Gain Step Setting LMAT1 0 ALC1 Limiter ATT Ste...

Page 55: ...lue at ALC1 Recovery Operation see Table 31 During the ALC1 recovery operation if the IPGA value exceeds the setting reference value by gain operation then the IPGA does not become larger than the ref...

Page 56: ...GR bit is changed to 1 When ALC1 bit is changed from 1 to 0 IPGA holds the last gain value set by ALC1 operation When IPGAL6 0 and IPGAR6 0 bits are read the register values written by the last write...

Page 57: ...fault 0 0 0 0 0 0 0 0 ATTS2 0 Attenuator select of signal from IPGA Lch to Stereo Mixer See Table 33 ATTS2 0 Attenuation 7H 6dB 6H 9dB 5H 12dB Default 4H 15dB 3H 18dB 2H 21dB 1H 24dB 0H 27dB Table 33...

Page 58: ...wn Power up Power up 1 0 Power up Power down Power up 1 1 Power up Power up Power up Table 34 ADC Block Power Control PMMICR MIC Power and IPGA Rch Block Power Control 0 Power down Default 1 Power up...

Page 59: ...RIN1 52 51 50 49 LIN1 BEEPL BEEPR 48 47 45 44 46 42 41 43 40 BEEPM LIN2 RIN2 MOUT MOUT LOUT ROUT MOUT2 MIN 39 38 37 36 35 34 33 32 31 30 29 28 27 MUTET HPL HPR HVSS HVDD SPN SPP M S XTI MCKI XTO DVSS...

Page 60: ...ed to the VCOM pin eliminates the effects of high frequency noise No load current may be drawn from the VCOM pin All signals especially clocks should be kept away from the VCOM pin in order to avoid u...

Page 61: ...2896 M H z 1 P ow er S u p p ly 2 P D N p in L o H 3 A d d r 0 0 H D ata 8 0 H 4 A d d r 0 2 H D ata 0 3 H 5 A d d r 0 3 H D ata 8 3 H 6 A d d r 0 4 H D ata 4 2 H Figure 48 Power Up Sequence Example 1...

Page 62: ...ata 4 A H 4 M C K O ou tpu t starts 5 B IC K and L R C K inp u t start 6 A d d r 0 4 H D ata 6 A H Figure 49 Clock Set Up Sequence 1 Example 1 Release the pull down of the XTI pin MCKPD bit 1 o 0 and...

Page 63: ...ta 4 0 H 2 A d d r 0 1 H D ata 6 0 H 3 A d d r 0 4 H D ata 6 A H 4 M C K O B IC K an d L R C K outpu t starts Figure 50 Clock Set Up Sequence 2 Example 1 Release the pull down of the XTI pin MCKPD bit...

Page 64: ...external M C LK 3 A d dr 01 H D ata 20H 5 M C K O ou tput starts 6 B IC K and LR C K inp ut start 7 A d dr 04 H D ata 6A H 4 A d dr 04 H D ata 4A H Figure 51 Clock Set Up Sequence 3 Example 1 Release...

Page 65: ...s 40ms lock time after the PMPLL bit 0 o 1 4 Enable MCKO output MCKO bit 0 o 1 and set up MCKO output frequency PS1 0 bits 5 MCKO BICK and LRCK are output after PLL lock time 5 External clock mode MCK...

Page 66: ...is PLL mode MIC and ADC should be powered up in consideration of PLL lock time after a sampling frequency is changed 2 Set up MIC input Addr 07H 3 Set up Timer Select for ALC1 Addr 08H 4 Set up REF va...

Page 67: ...ncy FS2 0 bits if PLL mode is used 2 Set up the low frequency boost level BST1 0 bits 3 Set up the digital volume Addr 0CH and 0DH At DATTC bit 1 default ATTL7 0 bits of Address 0CH control both Lch a...

Page 68: ...a 6 1 H P la yb a c k 2 A d d r 0 9 H D a ta 0 0 H 6 A d d r 0 5 H D a ta 6 0 H 7 A d d r 0 1 H D a ta 6 0 H Figure 56 Speaker Amp Output Sequence Example At first clocks should be supplied according...

Page 69: ...down the XTI pin PMXTL bit PMPLL bit 1 o 0 MCKPD 0 o 1 2 When an external clock is used in PLL mode MCKPD bit Addr 01H D7 External MCLK PMPLL bit Addr 01H D5 MCKO bit Addr 03H D4 Input 1 2 3 Exam ple...

Page 70: ...l down the XTI pin MCKPD 0 o 1 When the external MCLK becomes Hi Z or the external MCLK is input by AC couple MCKI pin should be pulled down 2 Stop an external MCLK Power down Power down VCOM PMVCM 1...

Page 71: ...80 0 20 0 00 13 1 52 40 27 39 27 39 40 52 13 1 14 26 0 20 0 10 0 20 45 45 0 05 M 4 C0 6 0 18 0 05 0 40 Note The part of black at four corners on reverse side must not be soldered and must be open Mat...

Page 72: ...ASAHI KASEI AK4537 MS0202 E 04 2005 04 72 MARKING 1 AK4537VN XXXXXXX AKM XXXXXXX Date code identifier 7 digits Downloaded from Elcodis com electronic components distributor...

Page 73: ...put signals are lower than the ALC1 Recovery Waiting Counter Reset Level the ALC1 recovery operation starts 56 Register Definitions ATTS2 0 bit 0 OFF 1 ON is removed 59 Analog Input centered around th...

Page 74: ...C1 bit is changed from 1 to 0 IPGA holds the last gain value set by ALC1 operation is added 43 Register Definitions PMBPM bit Even if PMBPM 0 the path is still connected between BEEPM and HP Amp BPMHP...

Page 75: ...mic PMMICR and PMADR bits also should be set to 0 is added IPGA gain is reset when PMMICL PMMICR PMIPGL PMIPGR 0 and then IPGA operation starts from the default value when PMMICL PMMICR PMIPGL or PMIP...

Page 76: ...no responsibility relating to any such use except with the express written consent of the Representative Director of AKM As used here a A hazard related device or system is one designed or intended fo...

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