ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
-
64
-
3. When an external clock is used in PLL mode. (Slave mode)
MCKPD bit
(Addr:01H, D7)
PS1-0 bits
(Addr:04H, D5-4)
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
MCKO pin
XX
00
(1)
Output
BICK, LRCK
(Slave Mode)
Input
External MCLK
Input
(2)
(3)
40ms(max)
(4)
(5)
(6)
(7)
E xa m p le :
A u d io I/F F o r m a t : I
2
S
B IC K f re q u e nc y a t M a s te r M o d e : 6 4 f s
I np u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s te r C lo c k F re q ue n c y : 6 4 f s
(1 ) A d d r:0 1 H , D a ta :0 0 H
(2 ) In p u t e xte rn a l M C L K
(3 ) A d d r:0 1 H , D a ta 2 0 H
(5 ) M C K O o u tp u t sta rts
(6 ) B IC K a n d L R C K in p u t s ta rt
(7 ) A d d r:0 4 H , D a ta 6 A H
(4 ) A d d r:0 4 H , D a ta 4 A H
Figure 51. Clock Set Up Sequence(3)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1”
o
“0”
(2) Input an external MCLK
(3) Power-up PLL : PMPLL bit = “0”
o
“1”
PLL needs 40ms lock time after the PMPLL bit = “0”
o
“1”.
(4) Enable MCKO output : MCKO bit = “0”
o
“1”
(5) MCKO is output after PLL lock time.
(6) Input BICK and LRCK that synchronized in the MCKO output.
(7) Set up MCKO output frequency (PS1-0 bits)
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
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