ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
-
44
-
Register Definitions
Addr
Register
Name
D7 D6 D5 D4 D3 D2 D1 D0
00H Power
Management
1 PMVCM PMBPS PMBPM
PMLO
PMMO
PMIPGL PMMICL
PMADL
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Default
0 0 0 0 0 0 0 0
PMADL: ADC Lch Block Power Control
0:
Power
down
(Default)
1:
Power
up
When the PMADL or PMADR bit changes from “0” to “1”, the initialization cycle (2081/fs=47.2ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
Analog Digital
PMADL PMADR
Lch Rch L/R
0
0
Power down
Power down
Power down
0
1
Power down
Power up
Power up
1
0
Power up
Power down
Power up
1
1
Power up
Power up
Power up
Table 22. ADC Block Power Control
PMMICL: MIC Power and IPGA Lch Block Power Control
0:
Power
down
(Default)
1:
Power
up
PMIPGL: IPGA Lch Block Power Control
0:
Power
down
(Default)
1:
Power
up
IPGA Lch Block is powered up if PMMICL or PMIPGL bit is “1” (see Table 23).
PMMICL PMIPGL
MIC-Amp
IPGA
0
0
Power down
Power down
0
1
Power down
Power up
1
0
Power up
Power up
1
1
Power up
Power up
Table 23. MIC-Amp and IPGA Lch Block Power Control
PMMO: Mono Line Out Power Control
0:
Power
down
(Default)
1:
Power
up
PMLO: Stereo Line Out Power Control
0:
Power
down
(Default)
1:
Power
up
PMBPM: Mono BEEP In Power Control
0:
Power
down
(Default)
1:
Power
up
Even if PMBPM= “0”, the path is still connected between BEEPM and HP/SPK-Amp. BPMHP and BPMSP
bits should be set to “0” to disconnect these paths, respectively.
PMBPS: Stereo BEEP In Power Control
0:
Power
down
(Default)
1:
Power
up
Even if PMBPS= “0”, the path is still connected between BEEPL/R and HP/SPK-Amp. BPSHP and BPSSP
bits should be set to “0” to disconnect these paths, respectively.
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