Agilent Technologies E1439, User Manual

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73
Agilent E1439 Programmer's Reference
Functions listed alphabetically
age1439_adc_divider
Determines which divider is applied to the ADC clock source. This description also includes the
query function:
age1439_adc_divider_get
VXI plug&play Syntax
#include "age1439".h
ViStatus age1439_adc_divider(ViSession id , ViInt16 adcDivider );
ViStatus age1439_adc_divider_get(ViSession id , ViPInt16 adcDividerPtr );
Note
This command should be used only for specialized custom clock requirements. Most useful clock
setups can be supplied by
age1439_clock_setup .
Description
This function should generally be left in the default mode. The alternate mode applies to a
different model of the module.
Parameters
id is the VXI instrument session pointer returned by the age1439_init function.
adcDivider AGE1439_DIVIDE_BY_10 divides the ADC clock by 10.
AGE1439_DIVIDE_BY_38 divides the ADC clock by 38.
adcDividerPtr points to the current value of adcDivider .
Return Value
AGE1439_SUCCESS indicates that a function was successful.
Values other than AGE1439_SUCCESS indicate an error condition or other important status
condition. To determine the error message, pass the return value to “age1439_error_message” on
page 102 .
Comments
The Agilent E1439 normally runs its sample clock at 95 MHz. It divides that clock by 38 to
generate 2.5 MHz, which can be compared against a user-supplied 10Mhz reference that we
internally divide by 4 (age1439_reference_prescaler) which also generates a 2.5 MHz clock. In
the case of a multi module system without an external reference clock, the master module sends
its 2.5 MHz clock out on the VXI bus or front panel smbs for use by the other module's PLLs.
See Also
“Default values” on page 201 , “age1439_init” on page 132 , “age1439_clock_setup” on page 78 ,
“Using clock and sync” in chapter 3