Agilent Technologies E1437A, User Manual, Page: 61 / 214

Parameters
id is the VXI instrument session pointer returned by the hpe1437_init function.
sync is used to specify whether the module uses a shared ADC clock and SYNC signal.
If the sync parameter is set to HPE1437_OFF the ADC clock and SYNC are generated
locally. If sync is set to HPE1437_REAR the module uses the shared ADC clock and
SYNC signals which are distributed on the VXI backplane using the ECL trigger lines. If
sync is set to HPE1437_FRONT the module uses the shared clock and SYNC provided
on the front panel distribution connectors. Modules in multi-module systems must all
have the same
sync
parameter setting.
syncPtr contains the current value of the sync parameter.
source selects the clock source that is used to drive the analog to digital converter
(ADC) for single module operation or when a module is used as the master ADC clock
source for a multi-module system. When set to
HPE1437_20000KHZ the clock source
is the internal 20 MHz oscillator. When set to HPE1437_20480KHZ the clock source is
the internal 20.48 MHz oscillator. HPE1437_EXTERNAL selects the TTL, ECL, or sine
signal on the external BNC front panel clock input connector. When using an external
clock the
fs
parameter is used to provide the module with the frequency of the external
clock. HPE1437_EXT_PLL_REF takes a 10 MHz reference fromanother instrument
on the external BNC front panel clock input connector and uses a PLL to convert it to a
20 MHz reference. In multi-module systems the
source parameter is ignored for all but
the master module.
sourcePtr contains the current value of the source parameter.
dsp selects the clock used to drive the decimation/zoom section within the E1437.
Normally, the DSP clock should be coupled to the ADC clock whenever possible since
the spurious performance specification is degraded when the clocks are independent.
However, when a slow or intermittent ADC clock results in greater than 1
µ
s between
clock edges, the DSP clock must be generated from the internal oscillator to avoid data
loss in the dynamic RAM. Setting this parameter to
HPE1437_ADC forces the DSP
clock to be driven by the ADC clock.
HPE1437_OSCILLATOR
will cause the DSP
clock to be the internally generated 20.48 MHz oscillator. Note that the computed
results will be the same in either case.
dspPtr contains the current value of the dsp parameter.
master determines whether an E1437 makes its local ADC clock available to other
modules as a shared clock. Multi-module synchronization requires one and only one of
the modules to be identified as the master, that is, the source of the shared ADC clock.
Setting this parameter to
HPE1437_ON when sync = HPE1437_FRONT causes the
E1437 to drive the front panel ADC clock; or if
sync
=
HPE1437_REAR
causes the
module to use its ADC clock to drive the VXI backplane in the mainframe in which it
resides.
HPE1437_OFF means that the E1437 is driving neither the front panel nor the
backplane and is the correct variable to use for all non-master modules in a
multi-module system. Setting this parameter to
HPE1437_BUFFER allows the ADC
clock and SYNC lines fromthe module’s front panel connectors to drive the backplane
of a mainframe not containing the master. Only one module per mainframe may be set
to
ON or to BUFFER . In multi-module and multi-mainframe systems only one module
may be set to ON within the entire system. In multi-mainframe systems using backplane
clock and sync distribution only one module per any mainframe not containing the
master may be set to
BUFFER .
masterPtr
contains the current value of the
master
parameter.
E1437A User's Guide
VXI
plug&play Programming Reference
4-14
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